Date: Mon, 22 Jul 2019 16:31:16 +0000 (UTC) From: Yuri Victorovich <yuri@FreeBSD.org> To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r507146 - in head/cad: . digital digital/files Message-ID: <201907221631.x6MGVGUo084429@repo.freebsd.org>
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Author: yuri Date: Mon Jul 22 16:31:16 2019 New Revision: 507146 URL: https://svnweb.freebsd.org/changeset/ports/507146 Log: New port: cad/digital: Digital logic designer and circuit simulator Added: head/cad/digital/ head/cad/digital/Makefile (contents, props changed) head/cad/digital/distinfo (contents, props changed) head/cad/digital/files/ head/cad/digital/files/patch-pom.xml (contents, props changed) head/cad/digital/pkg-descr (contents, props changed) Modified: head/cad/Makefile Modified: head/cad/Makefile ============================================================================== --- head/cad/Makefile Mon Jul 22 15:34:37 2019 (r507145) +++ head/cad/Makefile Mon Jul 22 16:31:16 2019 (r507146) @@ -18,6 +18,7 @@ SUBDIR += cascade SUBDIR += chipvault SUBDIR += cura-engine + SUBDIR += digital SUBDIR += dinotrace SUBDIR += dxf2fig SUBDIR += electric Added: head/cad/digital/Makefile ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/digital/Makefile Mon Jul 22 16:31:16 2019 (r507146) @@ -0,0 +1,62 @@ +# $FreeBSD$ + +PORTNAME= digital +DISTVERSIONPREFIX= v +DISTVERSION= 0.22 +CATEGORIES= cad java + +MAINTAINER= yuri@FreeBSD.org +COMMENT= Digital logic designer and circuit simulator + +LICENSE= GPLv3 +LICENSE_FILE= ${WRKSRC}/LICENSE + +BUILD_DEPENDS= mvn:devel/maven + +USE_JAVA= yes +USE_GITHUB= yes +GH_ACCOUNT= hneemann +GH_PROJECT= Digital + +NO_ARCH= yes + +# to rebuild the deps archive: +# 1. set DEV_UPDATE_MODE=yes +# 2. make makesum build +# 3. upload the *-deps archive +# 4. set DEV_UPDATE_MODE=no +# 5. make clean makesum + +DEV_UPDATE_MODE= no + +.if (${DEV_UPDATE_MODE} == "yes") +post-build: + @cd ${WRKDIR} && ${TAR} czf ${DISTDIR}/${PORTNAME}-${DISTVERSION}-deps${EXTRACT_SUFX} .m2 + @${ECHO} "(!!!) Please upload the maven deps archive: ${DISTDIR}/${PORTNAME}-${DISTVERSION}-deps${EXTRACT_SUFX}" +.else +MASTER_SITES+= LOCAL/yuri/:maven +DISTFILES+= ${PORTNAME}-${DISTVERSION}-deps${EXTRACT_SUFX}:maven +MVN_ARGS= --offline +.endif + +DESKTOP_ENTRIES= "Digital logic designer" "Digital logic designer and circuit simulator" "" "${PORTNAME}" "Electronics;" "" + +PLIST_FILES= bin/${PORTNAME} \ + ${JAVAJARDIR}/Digital.jar + +do-build: + @cd ${WRKSRC} && ${SETENV} ${MAKE_ENV} \ + ${LOCALBASE}/bin/mvn ${MVN_ARGS} \ + -fae install \ + -Dmaven.test.skip=true \ + -Duser.home=${WRKDIR} \ + package +do-install: + ${INSTALL_DATA} ${WRKSRC}/target/Digital.jar ${STAGEDIR}${JAVAJARDIR} + @(echo "#!/bin/sh"; \ + echo ""; \ + echo "${JAVA} -jar ${JAVAJARDIR}/Digital.jar \""$$"@\"" \ + ) > ${STAGEDIR}${PREFIX}/bin/${PORTNAME} + @${CHMOD} +x ${STAGEDIR}${PREFIX}/bin/${PORTNAME} + +.include <bsd.port.mk> Added: head/cad/digital/distinfo ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/digital/distinfo Mon Jul 22 16:31:16 2019 (r507146) @@ -0,0 +1,5 @@ +TIMESTAMP = 1563812653 +SHA256 (digital-0.22-deps.tar.gz) = 2898250162babda82352e34b36aef95010f5e973af9eb3fde78aa16745e54057 +SIZE (digital-0.22-deps.tar.gz) = 51278882 +SHA256 (hneemann-Digital-v0.22_GH0.tar.gz) = 445d2993785d1f5dd59c41aed6ea68d42ae7a83c6cb1d0c5037de44f2fc465dd +SIZE (hneemann-Digital-v0.22_GH0.tar.gz) = 3768846 Added: head/cad/digital/files/patch-pom.xml ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/digital/files/patch-pom.xml Mon Jul 22 16:31:16 2019 (r507146) @@ -0,0 +1,37 @@ +Maybe this can be entirely eliminated with new maven args: -P no-git-rev -Dgit.commit.id.describe=${DISTVERSION} + +--- pom.xml.orig 2019-07-22 05:00:43 UTC ++++ pom.xml +@@ -133,25 +133,6 @@ + </plugin> + + <plugin> +- <groupId>pl.project13.maven</groupId> +- <artifactId>git-commit-id-plugin</artifactId> +- <version>2.2.1</version> +- <executions> +- <execution> +- <id>get-the-git-infos</id> +- <goals> +- <goal>revision</goal> +- </goals> +- </execution> +- </executions> +- <configuration> +- <dotGitDirectory>${project.basedir}/.git</dotGitDirectory> +- <verbose>false</verbose> +- <commitIdGenerationMode>flat</commitIdGenerationMode> +- </configuration> +- </plugin> +- +- <plugin> + <groupId>org.apache.maven.plugins</groupId> + <artifactId>maven-checkstyle-plugin</artifactId> + <version>2.17</version> +@@ -330,4 +311,4 @@ + <connection>scm:git:file://localhost/${pom.basedir}</connection> + </scm> + +-</project> +\ No newline at end of file ++</project> Added: head/cad/digital/pkg-descr ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/digital/pkg-descr Mon Jul 22 16:31:16 2019 (r507146) @@ -0,0 +1,24 @@ +Features: +* Visualization of signal states with measurement graphs. +* Single gate mode to analyze oscillations. +* Analysis and synthesis of combinatorial and sequential circuits. +* Simple testing of circuits: You can create test cases and execute them to + verify your design. +* Includes a simple editor for finite state machines (FSM). A FSM can then be + converted to a state transition table and a circuit implementing the FSM. +* Contains a library with the most commonly used 74xx series integrated circuits +* Supports generic circuits. This allows the creation of circuits that can be + parameterized when used. In this way, it is possible, for e.g., to create a + barrel shifter with a selectable bit width. +* Supports large circuits: The "Conway's Game of Life" example consists of about + 2400 active components and works just fine. +* It is possible to use custom components which are implemented in Java and + packed in a jar file. See this example for details. +* Simple remote TCP interface which e.g. allows an assembler IDE to control the + simulator. +* Components can be described using VHDL or Verilog. The open source VHDL + simulator ghdl needs to be installed to simulate a VHDL defined component, and + the open source Verilog simulator Icarus Verilog is required to simulate a + Verilog defined component. + +WWW: https://github.com/hneemann/Digital
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