From owner-svn-ports-all@freebsd.org Mon Jul 22 16:31:17 2019 Return-Path: Delivered-To: svn-ports-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id AA3DDB5558; Mon, 22 Jul 2019 16:31:17 +0000 (UTC) (envelope-from yuri@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 8B23C76A4A; Mon, 22 Jul 2019 16:31:17 +0000 (UTC) (envelope-from yuri@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 63251FED7; Mon, 22 Jul 2019 16:31:17 +0000 (UTC) (envelope-from yuri@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x6MGVH8x084437; Mon, 22 Jul 2019 16:31:17 GMT (envelope-from yuri@FreeBSD.org) Received: (from yuri@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x6MGVGUo084429; Mon, 22 Jul 2019 16:31:16 GMT (envelope-from yuri@FreeBSD.org) Message-Id: <201907221631.x6MGVGUo084429@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: yuri set sender to yuri@FreeBSD.org using -f From: Yuri Victorovich Date: Mon, 22 Jul 2019 16:31:16 +0000 (UTC) To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r507146 - in head/cad: . digital digital/files X-SVN-Group: ports-head X-SVN-Commit-Author: yuri X-SVN-Commit-Paths: in head/cad: . digital digital/files X-SVN-Commit-Revision: 507146 X-SVN-Commit-Repository: ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 8B23C76A4A X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.97 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-1.000,0]; NEURAL_HAM_SHORT(-0.97)[-0.968,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US]; NEURAL_HAM_LONG(-1.00)[-1.000,0] X-BeenThere: svn-ports-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the ports tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 22 Jul 2019 16:31:17 -0000 Author: yuri Date: Mon Jul 22 16:31:16 2019 New Revision: 507146 URL: https://svnweb.freebsd.org/changeset/ports/507146 Log: New port: cad/digital: Digital logic designer and circuit simulator Added: head/cad/digital/ head/cad/digital/Makefile (contents, props changed) head/cad/digital/distinfo (contents, props changed) head/cad/digital/files/ head/cad/digital/files/patch-pom.xml (contents, props changed) head/cad/digital/pkg-descr (contents, props changed) Modified: head/cad/Makefile Modified: head/cad/Makefile ============================================================================== --- head/cad/Makefile Mon Jul 22 15:34:37 2019 (r507145) +++ head/cad/Makefile Mon Jul 22 16:31:16 2019 (r507146) @@ -18,6 +18,7 @@ SUBDIR += cascade SUBDIR += chipvault SUBDIR += cura-engine + SUBDIR += digital SUBDIR += dinotrace SUBDIR += dxf2fig SUBDIR += electric Added: head/cad/digital/Makefile ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/digital/Makefile Mon Jul 22 16:31:16 2019 (r507146) @@ -0,0 +1,62 @@ +# $FreeBSD$ + +PORTNAME= digital +DISTVERSIONPREFIX= v +DISTVERSION= 0.22 +CATEGORIES= cad java + +MAINTAINER= yuri@FreeBSD.org +COMMENT= Digital logic designer and circuit simulator + +LICENSE= GPLv3 +LICENSE_FILE= ${WRKSRC}/LICENSE + +BUILD_DEPENDS= mvn:devel/maven + +USE_JAVA= yes +USE_GITHUB= yes +GH_ACCOUNT= hneemann +GH_PROJECT= Digital + +NO_ARCH= yes + +# to rebuild the deps archive: +# 1. set DEV_UPDATE_MODE=yes +# 2. make makesum build +# 3. upload the *-deps archive +# 4. set DEV_UPDATE_MODE=no +# 5. make clean makesum + +DEV_UPDATE_MODE= no + +.if (${DEV_UPDATE_MODE} == "yes") +post-build: + @cd ${WRKDIR} && ${TAR} czf ${DISTDIR}/${PORTNAME}-${DISTVERSION}-deps${EXTRACT_SUFX} .m2 + @${ECHO} "(!!!) Please upload the maven deps archive: ${DISTDIR}/${PORTNAME}-${DISTVERSION}-deps${EXTRACT_SUFX}" +.else +MASTER_SITES+= LOCAL/yuri/:maven +DISTFILES+= ${PORTNAME}-${DISTVERSION}-deps${EXTRACT_SUFX}:maven +MVN_ARGS= --offline +.endif + +DESKTOP_ENTRIES= "Digital logic designer" "Digital logic designer and circuit simulator" "" "${PORTNAME}" "Electronics;" "" + +PLIST_FILES= bin/${PORTNAME} \ + ${JAVAJARDIR}/Digital.jar + +do-build: + @cd ${WRKSRC} && ${SETENV} ${MAKE_ENV} \ + ${LOCALBASE}/bin/mvn ${MVN_ARGS} \ + -fae install \ + -Dmaven.test.skip=true \ + -Duser.home=${WRKDIR} \ + package +do-install: + ${INSTALL_DATA} ${WRKSRC}/target/Digital.jar ${STAGEDIR}${JAVAJARDIR} + @(echo "#!/bin/sh"; \ + echo ""; \ + echo "${JAVA} -jar ${JAVAJARDIR}/Digital.jar \""$$"@\"" \ + ) > ${STAGEDIR}${PREFIX}/bin/${PORTNAME} + @${CHMOD} +x ${STAGEDIR}${PREFIX}/bin/${PORTNAME} + +.include Added: head/cad/digital/distinfo ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/digital/distinfo Mon Jul 22 16:31:16 2019 (r507146) @@ -0,0 +1,5 @@ +TIMESTAMP = 1563812653 +SHA256 (digital-0.22-deps.tar.gz) = 2898250162babda82352e34b36aef95010f5e973af9eb3fde78aa16745e54057 +SIZE (digital-0.22-deps.tar.gz) = 51278882 +SHA256 (hneemann-Digital-v0.22_GH0.tar.gz) = 445d2993785d1f5dd59c41aed6ea68d42ae7a83c6cb1d0c5037de44f2fc465dd +SIZE (hneemann-Digital-v0.22_GH0.tar.gz) = 3768846 Added: head/cad/digital/files/patch-pom.xml ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/digital/files/patch-pom.xml Mon Jul 22 16:31:16 2019 (r507146) @@ -0,0 +1,37 @@ +Maybe this can be entirely eliminated with new maven args: -P no-git-rev -Dgit.commit.id.describe=${DISTVERSION} + +--- pom.xml.orig 2019-07-22 05:00:43 UTC ++++ pom.xml +@@ -133,25 +133,6 @@ + + + +- pl.project13.maven +- git-commit-id-plugin +- 2.2.1 +- +- +- get-the-git-infos +- +- revision +- +- +- +- +- ${project.basedir}/.git +- false +- flat +- +- +- +- + org.apache.maven.plugins + maven-checkstyle-plugin + 2.17 +@@ -330,4 +311,4 @@ + scm:git:file://localhost/${pom.basedir} + + +- +\ No newline at end of file ++ Added: head/cad/digital/pkg-descr ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/digital/pkg-descr Mon Jul 22 16:31:16 2019 (r507146) @@ -0,0 +1,24 @@ +Features: +* Visualization of signal states with measurement graphs. +* Single gate mode to analyze oscillations. +* Analysis and synthesis of combinatorial and sequential circuits. +* Simple testing of circuits: You can create test cases and execute them to + verify your design. +* Includes a simple editor for finite state machines (FSM). A FSM can then be + converted to a state transition table and a circuit implementing the FSM. +* Contains a library with the most commonly used 74xx series integrated circuits +* Supports generic circuits. This allows the creation of circuits that can be + parameterized when used. In this way, it is possible, for e.g., to create a + barrel shifter with a selectable bit width. +* Supports large circuits: The "Conway's Game of Life" example consists of about + 2400 active components and works just fine. +* It is possible to use custom components which are implemented in Java and + packed in a jar file. See this example for details. +* Simple remote TCP interface which e.g. allows an assembler IDE to control the + simulator. +* Components can be described using VHDL or Verilog. The open source VHDL + simulator ghdl needs to be installed to simulate a VHDL defined component, and + the open source Verilog simulator Icarus Verilog is required to simulate a + Verilog defined component. + +WWW: https://github.com/hneemann/Digital