From owner-freebsd-stable Thu Aug 16 17:13:16 2001 Delivered-To: freebsd-stable@freebsd.org Received: from gull.mail.pas.earthlink.net (gull.mail.pas.earthlink.net [207.217.121.85]) by hub.freebsd.org (Postfix) with ESMTP id BB38E37B40B for ; Thu, 16 Aug 2001 17:13:13 -0700 (PDT) (envelope-from B-Morgan@concentric.net) Received: from cos80474 (cpe-24-221-198-127.co.sprintbbd.net [24.221.198.127]) by gull.mail.pas.earthlink.net (EL-8_9_3_3/8.9.3) with SMTP id RAA09845; Thu, 16 Aug 2001 17:13:11 -0700 (PDT) From: "Brad Morgan" To: "Paul" Cc: Subject: RE: New kernel option CPU_ENABLE_SSE Date: Thu, 16 Aug 2001 18:13:10 -0600 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook IMO, Build 9.0.2416 (9.0.2911.0) X-MIMEOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 In-reply-to: <20010816170035.A45250@tribble.net> Importance: Normal Sender: owner-freebsd-stable@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG Correct me if I'm wrong but I would suspect that kernel support for MMX, SSE, SSE2, etc. means at a minimum that any state generated by this set of instructions needs to be saved across context switches. Otherwise, two or more processes using those instructions at the same time might tend to get each other confused. -----Original Message----- From: owner-freebsd-stable@FreeBSD.ORG [mailto:owner-freebsd-stable@FreeBSD.ORG]On Behalf Of Paul Sent: Thursday, August 16, 2001 5:01 PM To: Kris Kennaway Cc: stable@FreeBSD.ORG Subject: Re: New kernel option CPU_ENABLE_SSE Once upon a time, Kris Kennaway scribed: > On Thu, Aug 16, 2001 at 06:00:40PM -0400, Kenneth W Cochran wrote: > > Am I correct in assuming that "older generation" 686 CPUs > > (i.e. pre-Pentium-III) don't support SSE & that SSE is a > > function/enhancement of "newer generation" CPUs? > > Yes. I think it came in with the Pentium III. Correct. Pentium III supports SSE, as well do the newer Celeron chips which are essentially PIIIs with less L2 cache. That's my understanding, anyhow. Don't know anything about SSE2. Considering how worthless PIVs are, really, does it matter? :P > Kris Regards, Paul http://www.tribble.net/ Bush - not popularly elected, making unpopular decisions against the will of the people. If you're not outraged, I guess you aren't paying attention. To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-stable" in the body of the message To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-stable" in the body of the message