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Date:      Thu, 16 May 1996 15:51:28 -1000
From:      richard@pegasus.com (Richard Foulk)
To:        "Rodney W. Grimes" <rgrimes@GndRsh.aac.dev.com>, jgreco@brasil.moneng.mei.com (Joe Greco)
Cc:        hackers@freebsd.org, hardware@freebsd.org
Subject:   Re: Triton chipset with 256k cache caches 32M only?
Message-ID:  <199605170151.PAA20303@pegasus.com>
In-Reply-To: "Rodney W. Grimes" <rgrimes@GndRsh.aac.dev.com> "Re: Triton chipset with 256k cache caches 32M only?" (May 15, 10:04am)

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} > > >>    No, it uses the parity bits. Only 8 syndrome bits are needed
} > > >> for 64bit words.
} > > >
} > > >	Hmm.  So does that mean the ECC is limited to single (odd
} > > >number of) bit errors?
} > > 
} > >   ECC has single bit error correction and 2 bit error detection. Better than
} > > parity no matter how you slice it.
} 
} Only if you have memory that is failing or you need extreamly reliable
} operation (good memory should have a single bit error rate of something
} like 1 in 10 years).

This is all subject to personal judgement.

How a 15% performance hit compares with the possibility of lost or bad
data should not be trivialized.  One error in ten years may not seem
like much, but it could still cost lots of time and money.  And it's
just as likely to happen today as in ten years.

Besides, parity protection doesn't prevent memory-error crashes, ECC does.

Having no protection is scarey (Triton-I).

Parity memory is a great improvement.

ECC is better yet.


Richard



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