From owner-freebsd-arch@FreeBSD.ORG Fri Oct 28 16:10:52 2011 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 5516D1065674; Fri, 28 Oct 2011 16:10:52 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id 139DD8FC12; Fri, 28 Oct 2011 16:10:51 +0000 (UTC) Received: from [10.30.101.53] ([209.117.142.2]) (authenticated bits=0) by harmony.bsdimp.com (8.14.4/8.14.3) with ESMTP id p9SG7Aeg036981 (version=TLSv1/SSLv3 cipher=DHE-DSS-AES128-SHA bits=128 verify=NO); Fri, 28 Oct 2011 10:07:11 -0600 (MDT) (envelope-from imp@bsdimp.com) Mime-Version: 1.0 (Apple Message framework v1084) Content-Type: text/plain; charset=us-ascii From: Warner Losh In-Reply-To: <201110280915.18111.hselasky@c2i.net> Date: Fri, 28 Oct 2011 10:04:56 -0600 Content-Transfer-Encoding: quoted-printable Message-Id: References: <201110280915.18111.hselasky@c2i.net> To: Hans Petter Selasky X-Mailer: Apple Mail (2.1084) X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.0.1 (harmony.bsdimp.com [10.0.0.6]); Fri, 28 Oct 2011 10:07:12 -0600 (MDT) Cc: Adrian Chadd , freebsd-arch@freebsd.org Subject: Re: newbus IO ordering semantics - moving forward X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Oct 2011 16:10:52 -0000 On Oct 28, 2011, at 1:15 AM, Hans Petter Selasky wrote: > On Thursday 27 October 2011 22:28:13 Adrian Chadd wrote: >> * Make the bus default to use ordered semantics, much like what Linux >> does - ie, all IO read/writes (io or memory) are in-order and flushed >> with a barrier; >=20 > I think this is the assumption of many USB controller drivers = currently in the=20 > tree. The ordering guarantees aren't as random as Adrian suggests. All writes = are posted before any reads is about all you can count on. Most drivers = naturally cope with this well. All reads have to be synchronous by = their very nature and in-order. There's more liberty taken with writes = wrt ordering. Where it falls down is DMA or MSI. Both of those have writes from the = device to the system memory, and ordering of the completion of those = relative to other things isn't completely guaranteed. Warner