From owner-svn-src-head@FreeBSD.ORG Thu Dec 6 21:53:23 2012 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 76722691; Thu, 6 Dec 2012 21:53:23 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from bigwig.baldwin.cx (bigknife-pt.tunnel.tserv9.chi1.ipv6.he.net [IPv6:2001:470:1f10:75::2]) by mx1.freebsd.org (Postfix) with ESMTP id 4850A8FC16; Thu, 6 Dec 2012 21:53:23 +0000 (UTC) Received: from pakbsde14.localnet (unknown [38.105.238.108]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id A1717B977; Thu, 6 Dec 2012 16:53:22 -0500 (EST) From: John Baldwin To: Andriy Gapon Subject: Re: svn commit: r243764 - head/sys/x86/x86 Date: Thu, 6 Dec 2012 15:40:42 -0500 User-Agent: KMail/1.13.5 (FreeBSD/8.2-CBSD-20110714-p22; KDE/4.5.5; amd64; ; ) References: <201212011816.qB1IGE2Y064317@svn.freebsd.org> In-Reply-To: <201212011816.qB1IGE2Y064317@svn.freebsd.org> MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <201212061540.42393.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.7 (bigwig.baldwin.cx); Thu, 06 Dec 2012 16:53:22 -0500 (EST) Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Dec 2012 21:53:23 -0000 On Saturday, December 01, 2012 1:16:14 pm Andriy Gapon wrote: > Author: avg > Date: Sat Dec 1 18:16:14 2012 > New Revision: 243764 > URL: http://svnweb.freebsd.org/changeset/base/243764 > > Log: > ioapic_program_intpin: program high bits before low bits > > Programming the low bits has a side-effect if unmasking the pin if it is > not disabled. So if an interrupt was pending then it would be delivered > with the correct new vector but to the incorrect old LAPIC. > > This fix could be made clearer by preserving the mask bit while > programming the low bits and then explicitly resetting the mask bit > after all the programming is done. > > Probability to trip over the fixed bug could be increased by bootverbose > because printing of the interrupt information in ioapic_assign_cpu > lengthened the time window during which an interrupt could arrive while > a pin is masked. Can you expand the comment to say that you write 'low' second since it may clear the masked bit? -- John Baldwin