From owner-svn-src-head@freebsd.org Wed May 17 21:14:29 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 42228D714E4; Wed, 17 May 2017 21:14:29 +0000 (UTC) (envelope-from loos@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 1A2038F4; Wed, 17 May 2017 21:14:29 +0000 (UTC) (envelope-from loos@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v4HLESEh036564; Wed, 17 May 2017 21:14:28 GMT (envelope-from loos@FreeBSD.org) Received: (from loos@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v4HLESDA036563; Wed, 17 May 2017 21:14:28 GMT (envelope-from loos@FreeBSD.org) Message-Id: <201705172114.v4HLESDA036563@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: loos set sender to loos@FreeBSD.org using -f From: Luiz Otavio O Souza Date: Wed, 17 May 2017 21:14:28 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r318426 - head/sys/arm/mv X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 17 May 2017 21:14:29 -0000 Author: loos Date: Wed May 17 21:14:27 2017 New Revision: 318426 URL: https://svnweb.freebsd.org/changeset/base/318426 Log: Use the MACROS to access the Global mpic registers. Makes the code consistent and easier to read. While here, remove two unused static functions and fix a unused function warning when building !INTRNG. No functional changes. Sponsored by: Rubicon Communications, LLC (Netgate) Modified: head/sys/arm/mv/mpic.c Modified: head/sys/arm/mv/mpic.c ============================================================================== --- head/sys/arm/mv/mpic.c Wed May 17 20:23:27 2017 (r318425) +++ head/sys/arm/mv/mpic.c Wed May 17 21:14:27 2017 (r318426) @@ -148,12 +148,10 @@ static void mpic_unmask_irq(uintptr_t nb static void mpic_mask_irq(uintptr_t nb); static void mpic_mask_irq_err(uintptr_t nb); static void mpic_unmask_irq_err(uintptr_t nb); +#ifdef INTRNG static int mpic_intr(void *arg); -static void mpic_unmask_msi(void); -#ifndef INTRNG -static void arm_mask_irq_err(uintptr_t); -static void arm_unmask_irq_err(uintptr_t); #endif +static void mpic_unmask_msi(void); #define MPIC_WRITE(softc, reg, val) \ bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val)) @@ -260,8 +258,7 @@ mv_mpic_attach(device_t dev) sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]); } - bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, - MPIC_CTRL, 1); + MPIC_WRITE(mv_mpic_sc, MPIC_CTRL, 1); MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0); val = MPIC_READ(mv_mpic_sc, MPIC_CTRL); @@ -435,27 +432,12 @@ arm_mask_irq(uintptr_t nb) mpic_mask_irq(nb); } - -static void -arm_mask_irq_err(uintptr_t nb) -{ - - mpic_mask_irq_err(nb); -} - void arm_unmask_irq(uintptr_t nb) { mpic_unmask_irq(nb); } - -void -arm_unmask_irq_err(uintptr_t nb) -{ - - mpic_unmask_irq_err(nb); -} #endif static void @@ -471,8 +453,7 @@ mpic_unmask_irq_err(uintptr_t nb) uint32_t mask; uint8_t bit_off; - bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, - MPIC_ISE, MPIC_INT_ERR); + MPIC_WRITE(mv_mpic_sc, MPIC_ISE, MPIC_INT_ERR); MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR); bit_off = nb - ERR_IRQ; @@ -498,8 +479,7 @@ mpic_unmask_irq(uintptr_t nb) { if (nb < ERR_IRQ) { - bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, - MPIC_ISE, nb); + MPIC_WRITE(mv_mpic_sc, MPIC_ISE, nb); MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); } else if (nb < MSI_IRQ) mpic_unmask_irq_err(nb); @@ -513,8 +493,7 @@ mpic_mask_irq(uintptr_t nb) { if (nb < ERR_IRQ) { - bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, - MPIC_ICE, nb); + MPIC_WRITE(mv_mpic_sc, MPIC_ICE, nb); MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); } else if (nb < MSI_IRQ) mpic_mask_irq_err(nb); @@ -533,8 +512,7 @@ mv_mpic_get_cause_err(void) uint32_t err_cause; uint8_t bit_off; - err_cause = bus_space_read_4(mv_mpic_sc->mpic_bst, - mv_mpic_sc->mpic_bsh, MPIC_ERR_CAUSE); + err_cause = MPIC_READ(mv_mpic_sc, MPIC_ERR_CAUSE); if (err_cause) bit_off = ffs(err_cause) - 1; @@ -615,8 +593,7 @@ pic_ipi_send(cpuset_t cpus, u_int ipi) if (CPU_ISSET(i, &cpus)) val |= (1 << (8 + i)); val |= ipi; - bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, - MPIC_SOFT_INT, val); + MPIC_WRITE(mv_mpic_sc, MPIC_SOFT_INT, val); } int