From owner-freebsd-arch@FreeBSD.ORG Tue Apr 14 06:53:34 2009 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 1A850106564A for ; Tue, 14 Apr 2009 06:53:34 +0000 (UTC) (envelope-from zec@freebsd.org) Received: from labs4.cc.fer.hr (labs4.cc.fer.hr [161.53.72.24]) by mx1.freebsd.org (Postfix) with ESMTP id A14408FC16 for ; Tue, 14 Apr 2009 06:53:33 +0000 (UTC) (envelope-from zec@freebsd.org) Received: from sluga.fer.hr (sluga.cc.fer.hr [161.53.72.14]) by labs4.cc.fer.hr (8.14.2/8.14.2) with ESMTP id n3E6hIIW008709 for ; Tue, 14 Apr 2009 08:43:18 +0200 (CEST) Received: from [192.168.200.100] ([161.53.19.79]) by sluga.fer.hr with Microsoft SMTPSVC(6.0.3790.3959); Tue, 14 Apr 2009 08:42:55 +0200 From: Marko Zec To: freebsd-arch@freebsd.org Date: Tue, 14 Apr 2009 08:42:46 +0200 User-Agent: KMail/1.9.10 References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200904140842.46501.zec@freebsd.org> X-OriginalArrivalTime: 14 Apr 2009 06:42:55.0232 (UTC) FILETIME=[3DC32800:01C9BCCC] X-Scanned-By: MIMEDefang 2.64 on 161.53.72.24 Subject: Re: Simple #define for cache line size X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Apr 2009 06:53:34 -0000 On Monday 13 April 2009 23:01:23 Ivan Voras wrote: > Robert Watson wrote: > > --- i386/include/param.h (revision 190941) > > +++ i386/include/param.h (working copy) > > @@ -74,6 +74,10 @@ > > #define ALIGNBYTES _ALIGNBYTES > > #define ALIGN(p) _ALIGN(p) > > > > +#ifndef CACHE_LINE_SIZE > > +#define CACHE_LINE_SIZE 64 > > +#endif > > Wouldn't it be better to continue the > > cpu I486_CPU > cpu I586_CPU > cpu I686_CPU > > series of defines in kernel configuration and define alignment per > CPU architecture? We would have to extend our notion of "CPU architecture" for that to make sense. For example, Pentium Pro / II CPUs had cache line size of 32 bytes, Intel Netburst CPUs (all Pentium-4 and Xeons of the time) have / had 128 bytes, while Pentium-III, Pentium-M and later Core CPUs have 64 bytes. They are all I686_CPU in our view. Marko > I guess it depends on the trends - are cache lines > expected to change in the near future? :)