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To: Stephen Roome <steve@visint.co.uk>
cc: Michael Hancock <michaelh@cet.co.jp>,
        Darren Reed <avalon@coombs.anu.edu.au>,
        Terry Lambert <terry@lambert.org>, hackers@freebsd.org
From: "Louis A. Mamakos" <louie@TransSys.COM>
Subject: Re: 430TX ? 
References: <Pine.BSF.3.91.970411132308.11730L-100000@bagpuss.visint.co.uk> 
In-reply-to: Your message of "Fri, 11 Apr 1997 13:25:28 BST."
             <Pine.BSF.3.91.970411132308.11730L-100000@bagpuss.visint.co.uk> 
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Date: Fri, 11 Apr 1997 10:37:46 -0400
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> On Fri, 11 Apr 1997, Michael Hancock wrote:
> > While we're talking about Intel, they claim that they're focusing more on
> > memory bandwidth these days and the Pentium II has some kind of dual bus
> > architecture that makes a significant performance difference.
> 
> This is interesting, CTCM (motherboard benchmarker program) seems to tell 
> me that I can get almost 56MB/s memory bandwidth. With a 66MHz bus clock 
> I can't see how that this figure can improve much. Seeing as Intel seem 
> unlikely to support a 75MHz or 83MHz bus speed then I'd love to know how 
> they intend on doing this.

You could build 2- or 4-way interleaved memory banks, so that you could overlap
sequential memory fetches (like cache line fills).  This would be an
as an alternative to wider memory.  Some systems have *very* wide paths
to memory, approaching the width of a cache line, in fact.  Though I suspect
that it would be "easier" to make I/O and other bus-master access go faster
using the multiple memory bank approach.

This technique certainly isn't new - it's at least 25 years old.

louie