From owner-svn-src-all@FreeBSD.ORG Thu Feb 23 05:10:01 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 2F745106566B; Thu, 23 Feb 2012 05:10:01 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 1705B8FC0A; Thu, 23 Feb 2012 05:10:01 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q1N5A08q084804; Thu, 23 Feb 2012 05:10:00 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q1N5A0Ie084802; Thu, 23 Feb 2012 05:10:00 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <201202230510.q1N5A0Ie084802@svn.freebsd.org> From: Pyun YongHyeon Date: Thu, 23 Feb 2012 05:10:00 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r232019 - head/sys/dev/sf X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Feb 2012 05:10:01 -0000 Author: yongari Date: Thu Feb 23 05:10:00 2012 New Revision: 232019 URL: http://svn.freebsd.org/changeset/base/232019 Log: Give hardware chance to drain active DMA cycles. Modified: head/sys/dev/sf/if_sf.c Modified: head/sys/dev/sf/if_sf.c ============================================================================== --- head/sys/dev/sf/if_sf.c Thu Feb 23 04:32:41 2012 (r232018) +++ head/sys/dev/sf/if_sf.c Thu Feb 23 05:10:00 2012 (r232019) @@ -2329,6 +2329,9 @@ sf_stop(struct sf_softc *sc) /* Disable Tx/Rx egine. */ csr_write_4(sc, SF_GEN_ETH_CTL, 0); + /* Give hardware chance to drain active DMA cycles. */ + DELAY(1000); + csr_write_4(sc, SF_CQ_CONSIDX, 0); csr_write_4(sc, SF_CQ_PRODIDX, 0); csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);