From owner-svn-src-all@freebsd.org Wed Jan 29 08:46:36 2020 Return-Path: Delivered-To: svn-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 558001C724B; Wed, 29 Jan 2020 08:46:36 +0000 (UTC) (envelope-from ganbold@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 486xt41Xztz4Jh6; Wed, 29 Jan 2020 08:46:36 +0000 (UTC) (envelope-from ganbold@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 302C6968B; Wed, 29 Jan 2020 08:46:36 +0000 (UTC) (envelope-from ganbold@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 00T8kaqV036052; Wed, 29 Jan 2020 08:46:36 GMT (envelope-from ganbold@FreeBSD.org) Received: (from ganbold@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 00T8kaaw036051; Wed, 29 Jan 2020 08:46:36 GMT (envelope-from ganbold@FreeBSD.org) Message-Id: <202001290846.00T8kaaw036051@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: ganbold set sender to ganbold@FreeBSD.org using -f From: Ganbold Tsagaankhuu Date: Wed, 29 Jan 2020 08:46:36 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r357250 - head/sys/arm64/rockchip/clk X-SVN-Group: head X-SVN-Commit-Author: ganbold X-SVN-Commit-Paths: head/sys/arm64/rockchip/clk X-SVN-Commit-Revision: 357250 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Jan 2020 08:46:36 -0000 Author: ganbold Date: Wed Jan 29 08:46:35 2020 New Revision: 357250 URL: https://svnweb.freebsd.org/changeset/base/357250 Log: Add USB3 related clock definitions for Rockchip RK3328 SoC. Reviewed by: manu Modified: head/sys/arm64/rockchip/clk/rk3328_cru.c Modified: head/sys/arm64/rockchip/clk/rk3328_cru.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk3328_cru.c Wed Jan 29 05:59:22 2020 (r357249) +++ head/sys/arm64/rockchip/clk/rk3328_cru.c Wed Jan 29 08:46:35 2020 (r357250) @@ -51,6 +51,8 @@ __FBSDID("$FreeBSD$"); /* GATES */ +#define SCLK_USB3OTG_REF 96 +#define ACLK_USB3OTG 132 #define ACLK_PERI 153 #define PCLK_GPIO0 200 #define PCLK_GPIO1 201 @@ -61,6 +63,9 @@ __FBSDID("$FreeBSD$"); #define PCLK_I2C2 207 #define PCLK_I2C3 208 #define PCLK_TSADC 213 +#define PCLK_USB3PHY_OTG 224 +#define PCLK_USB3PHY_PIPE 225 +#define PCLK_USB3_GRF 226 #define HCLK_SDMMC 317 #define HCLK_SDIO 318 #define HCLK_EMMC 319 @@ -76,6 +81,7 @@ static struct rk_cru_gate rk3328_gates[] = { /* CRU_CLKGATE_CON4 */ CRU_GATE(0, "gpll_peri", "gpll", 0x210, 0) CRU_GATE(0, "cpll_peri", "cpll", 0x210, 1) + CRU_GATE(SCLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0x210, 7) /* CRU_CLKGATE_CON8 */ CRU_GATE(0, "pclk_bus", "pclk_bus_pre", 0x220, 3) @@ -98,13 +104,21 @@ static struct rk_cru_gate rk3328_gates[] = { CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0x240, 9) CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0x240, 10) + /* CRU_CLKGATE_CON17 */ + CRU_GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", 0x244, 2) + /* CRU_CLKGATE_CON19 */ CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0x24C, 0) CRU_GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0x24C, 1) CRU_GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0x24C, 2) CRU_GATE(0, "hclk_peri_niu", "hclk_peri", 0x24C, 12) CRU_GATE(0, "pclk_peri_niu", "hclk_peri", 0x24C, 13) + CRU_GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0x24C, 14) CRU_GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0x24C, 15) + + /* CRU_CLKGATE_CON28 */ + CRU_GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0x270, 1) + CRU_GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0x270, 2) }; /* @@ -991,6 +1005,78 @@ static struct rk_clk_composite_def i2c3 = { .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; +#define SCLK_USB3_REF 72 +#define SCLK_USB3_SUSPEND 73 +#define SCLK_USB3PHY_REF 94 +#define SCLK_REF_USB3OTG 95 +#define SCLK_USB3OTG_SUSPEND 97 +#define SCLK_REF_USB3OTG_SRC 98 + +static const char *ref_usb3otg_parents[] = { "xin24m", "clk_usb3otg_ref" }; + +static struct rk_clk_composite_def ref_usb3otg = { + .clkdef = { + .id = SCLK_REF_USB3OTG, + .name = "clk_ref_usb3otg", + .parent_names = ref_usb3otg_parents, + .parent_cnt = nitems(ref_usb3otg_parents), + }, + .muxdiv_offset = 0x1B4, + + .mux_shift = 8, + .mux_width = 1, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX, +}; + +static const char *usb3otg_suspend_parents[] = { "xin24m"/*, "clk_rtc32k" */}; + +static struct rk_clk_composite_def usb3otg_suspend = { + .clkdef = { + .id = SCLK_USB3OTG_SUSPEND, + .name = "clk_usb3otg_suspend", + .parent_names = usb3otg_suspend_parents, + .parent_cnt = nitems(usb3otg_suspend_parents), + }, + .muxdiv_offset = 0x184, + + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 0, + .div_width = 10, + + /* CRU_CLKGATE_CON4 */ + .gate_offset = 0x210, + .gate_shift = 8, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static const char *ref_usb3otg_src_parents[] = { "cpll", "gpll" }; + +static struct rk_clk_composite_def ref_usb3otg_src = { + .clkdef = { + .id = SCLK_REF_USB3OTG_SRC, + .name = "clk_ref_usb3otg_src", + .parent_names = ref_usb3otg_src_parents, + .parent_cnt = nitems(ref_usb3otg_src_parents), + }, + .muxdiv_offset = 0x1B4, + + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 7, + + /* CRU_CLKGATE_CON4 */ + .gate_offset = 0x210, + .gate_shift = 9, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + static struct rk_clk rk3328_clks[] = { { .type = RK3328_CLK_PLL, @@ -1075,6 +1161,19 @@ static struct rk_clk rk3328_clks[] = { { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c3 + }, + + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &ref_usb3otg + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &ref_usb3otg_src + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &usb3otg_suspend }, };