Date: Tue, 28 Jan 2020 11:33:13 +0000 (UTC) From: Konstantin Belousov <kib@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r357200 - in stable/12: stand/i386/libi386 sys/amd64/amd64 sys/i386/i386 sys/x86/cpufreq sys/x86/include sys/x86/x86 Message-ID: <202001281133.00SBXDNl069043@repo.freebsd.org>
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Author: kib Date: Tue Jan 28 11:33:12 2020 New Revision: 357200 URL: https://svnweb.freebsd.org/changeset/base/357200 Log: MFC r356940: Add support for Hygon Dhyana Family 18h processor. Modified: stable/12/stand/i386/libi386/bootinfo64.c stable/12/sys/amd64/amd64/initcpu.c stable/12/sys/i386/i386/machdep.c stable/12/sys/x86/cpufreq/hwpstate.c stable/12/sys/x86/include/cputypes.h stable/12/sys/x86/include/specialreg.h stable/12/sys/x86/x86/identcpu.c stable/12/sys/x86/x86/local_apic.c stable/12/sys/x86/x86/mca.c stable/12/sys/x86/x86/mp_x86.c stable/12/sys/x86/x86/msi.c stable/12/sys/x86/x86/tsc.c Directory Properties: stable/12/ (props changed) Modified: stable/12/stand/i386/libi386/bootinfo64.c ============================================================================== --- stable/12/stand/i386/libi386/bootinfo64.c Tue Jan 28 11:29:06 2020 (r357199) +++ stable/12/stand/i386/libi386/bootinfo64.c Tue Jan 28 11:33:12 2020 (r357200) @@ -158,6 +158,7 @@ bi_checkcpu(void) /* Check for vendors that support AMD features. */ if (strncmp(cpu_vendor, INTEL_VENDOR_ID, 12) != 0 && strncmp(cpu_vendor, AMD_VENDOR_ID, 12) != 0 && + strncmp(cpu_vendor, HYGON_VENDOR_ID, 12) != 0 && strncmp(cpu_vendor, CENTAUR_VENDOR_ID, 12) != 0) return (0); Modified: stable/12/sys/amd64/amd64/initcpu.c ============================================================================== --- stable/12/sys/amd64/amd64/initcpu.c Tue Jan 28 11:29:06 2020 (r357199) +++ stable/12/sys/amd64/amd64/initcpu.c Tue Jan 28 11:33:12 2020 (r357200) @@ -171,7 +171,8 @@ init_amd(void) */ if (lower_sharedpage_init == 0) { lower_sharedpage_init = 1; - if (CPUID_TO_FAMILY(cpu_id) == 0x17) { + if (CPUID_TO_FAMILY(cpu_id) == 0x17 || + CPUID_TO_FAMILY(cpu_id) == 0x18) { hw_lower_amd64_sharedpage = 1; } } @@ -259,6 +260,7 @@ initializecpu(void) amd64_syscall_ret_flush_l1d_recalc(); switch (cpu_vendor_id) { case CPU_VENDOR_AMD: + case CPU_VENDOR_HYGON: init_amd(); break; case CPU_VENDOR_CENTAUR: Modified: stable/12/sys/i386/i386/machdep.c ============================================================================== --- stable/12/sys/i386/i386/machdep.c Tue Jan 28 11:29:06 2020 (r357199) +++ stable/12/sys/i386/i386/machdep.c Tue Jan 28 11:33:12 2020 (r357200) @@ -1621,8 +1621,9 @@ DB_SHOW_COMMAND(sysregs, db_show_sysregs) if (cpu_feature2 & (CPUID2_VMX | CPUID2_SMX)) db_printf("FEATURES_CTL\t0x%016llx\n", rdmsr(MSR_IA32_FEATURE_CONTROL)); - if ((cpu_vendor_id == CPU_VENDOR_INTEL || - cpu_vendor_id == CPU_VENDOR_AMD) && CPUID_TO_FAMILY(cpu_id) >= 6) + if (((cpu_vendor_id == CPU_VENDOR_INTEL || + cpu_vendor_id == CPU_VENDOR_AMD) && CPUID_TO_FAMILY(cpu_id) >= 6) || + cpu_vendor_id == CPU_VENDOR_HYGON) db_printf("DEBUG_CTL\t0x%016llx\n", rdmsr(MSR_DEBUGCTLMSR)); if (cpu_feature & CPUID_PAT) db_printf("PAT\t0x%016llx\n", rdmsr(MSR_PAT)); Modified: stable/12/sys/x86/cpufreq/hwpstate.c ============================================================================== --- stable/12/sys/x86/cpufreq/hwpstate.c Tue Jan 28 11:29:06 2020 (r357199) +++ stable/12/sys/x86/cpufreq/hwpstate.c Tue Jan 28 11:33:12 2020 (r357200) @@ -315,7 +315,8 @@ hwpstate_identify(driver_t *driver, device_t parent) if (device_find_child(parent, "hwpstate", -1) != NULL) return; - if (cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10) + if ((cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10) && + cpu_vendor_id != CPU_VENDOR_HYGON) return; /* @@ -446,6 +447,7 @@ hwpstate_get_info_from_msr(device_t dev) hwpstate_set[i].freq = (100 * (fid + 0x10)) >> did; break; case 0x17: + case 0x18: did = AMD_17H_CUR_DID(msr); if (did == 0) { HWPSTATE_DEBUG(dev, "unexpected did: 0\n"); @@ -455,8 +457,10 @@ hwpstate_get_info_from_msr(device_t dev) hwpstate_set[i].freq = (200 * fid) / did; break; default: - HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family" - " 0x%02x CPUs are not supported yet\n", family); + HWPSTATE_DEBUG(dev, "get_info_from_msr: %s family" + " 0x%02x CPUs are not supported yet\n", + cpu_vendor_id == CPU_VENDOR_HYGON ? "Hygon" : "AMD", + family); return (ENXIO); } hwpstate_set[i].pstate_id = i; Modified: stable/12/sys/x86/include/cputypes.h ============================================================================== --- stable/12/sys/x86/include/cputypes.h Tue Jan 28 11:29:06 2020 (r357199) +++ stable/12/sys/x86/include/cputypes.h Tue Jan 28 11:33:12 2020 (r357200) @@ -45,5 +45,6 @@ #define CPU_VENDOR_INTEL 0x8086 /* Intel */ #define CPU_VENDOR_RISE 0xdead2bad /* Rise */ #define CPU_VENDOR_CENTAUR CPU_VENDOR_IDT +#define CPU_VENDOR_HYGON 0x1d94 /* Hygon */ #endif /* !_X86_CPUTYPES_H_ */ Modified: stable/12/sys/x86/include/specialreg.h ============================================================================== --- stable/12/sys/x86/include/specialreg.h Tue Jan 28 11:29:06 2020 (r357199) +++ stable/12/sys/x86/include/specialreg.h Tue Jan 28 11:33:12 2020 (r357200) @@ -468,6 +468,7 @@ #define SIS_VENDOR_ID "SiS SiS SiS " #define TRANSMETA_VENDOR_ID "GenuineTMx86" #define UMC_VENDOR_ID "UMC UMC UMC " +#define HYGON_VENDOR_ID "HygonGenuine" /* * Model-specific registers for the i386 family Modified: stable/12/sys/x86/x86/identcpu.c ============================================================================== --- stable/12/sys/x86/x86/identcpu.c Tue Jan 28 11:29:06 2020 (r357199) +++ stable/12/sys/x86/x86/identcpu.c Tue Jan 28 11:33:12 2020 (r357200) @@ -215,6 +215,7 @@ static struct { } cpu_vendors[] = { { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ + { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine*/ { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ #ifdef __i386__ { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ @@ -674,6 +675,18 @@ printcpuinfo(void) } break; #endif + case CPU_VENDOR_HYGON: + strcpy(cpu_model, "Hygon "); +#ifdef __i386__ + strcat(cpu_model, "Unknown"); +#else + if ((cpu_id & 0xf00) == 0xf00) + strcat(cpu_model, "AMD64 Processor"); + else + strcat(cpu_model, "Unknown"); +#endif + break; + default: strcat(cpu_model, "Unknown"); break; @@ -733,6 +746,7 @@ printcpuinfo(void) if (cpu_vendor_id == CPU_VENDOR_INTEL || cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_HYGON || cpu_vendor_id == CPU_VENDOR_CENTAUR || #ifdef __i386__ cpu_vendor_id == CPU_VENDOR_TRANSMETA || @@ -1051,7 +1065,8 @@ printcpuinfo(void) print_svm_info(); if ((cpu_feature & CPUID_HTT) && - cpu_vendor_id == CPU_VENDOR_AMD) + (cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_HYGON)) cpu_feature &= ~CPUID_HTT; /* @@ -1081,7 +1096,8 @@ printcpuinfo(void) printf("\n"); if (bootverbose) { - if (cpu_vendor_id == CPU_VENDOR_AMD) + if (cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_HYGON) print_AMD_info(); else if (cpu_vendor_id == CPU_VENDOR_INTEL) print_INTEL_info(); @@ -1520,6 +1536,7 @@ finishidentcpu(void) if (cpu_high > 0 && (cpu_vendor_id == CPU_VENDOR_INTEL || cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_HYGON || cpu_vendor_id == CPU_VENDOR_TRANSMETA || cpu_vendor_id == CPU_VENDOR_CENTAUR || cpu_vendor_id == CPU_VENDOR_NSC)) { @@ -1530,6 +1547,7 @@ finishidentcpu(void) #else if (cpu_vendor_id == CPU_VENDOR_INTEL || cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_HYGON || cpu_vendor_id == CPU_VENDOR_CENTAUR) { do_cpuid(0x80000000, regs); cpu_exthigh = regs[0]; @@ -1649,7 +1667,8 @@ int pti_get_default(void) { - if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0) + if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 || + strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0) return (0); if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0) return (0); Modified: stable/12/sys/x86/x86/local_apic.c ============================================================================== --- stable/12/sys/x86/x86/local_apic.c Tue Jan 28 11:29:06 2020 (r357199) +++ stable/12/sys/x86/x86/local_apic.c Tue Jan 28 11:33:12 2020 (r357200) @@ -676,7 +676,8 @@ amd_read_ext_features(void) { uint32_t version; - if (cpu_vendor_id != CPU_VENDOR_AMD) + if (cpu_vendor_id != CPU_VENDOR_AMD && + cpu_vendor_id != CPU_VENDOR_HYGON) return (0); version = lapic_read32(LAPIC_VERSION); if ((version & APIC_VER_AMD_EXT_SPACE) != 0) Modified: stable/12/sys/x86/x86/mca.c ============================================================================== --- stable/12/sys/x86/x86/mca.c Tue Jan 28 11:29:06 2020 (r357199) +++ stable/12/sys/x86/x86/mca.c Tue Jan 28 11:33:12 2020 (r357200) @@ -134,7 +134,8 @@ static int amd_elvt = -1; static inline bool amd_thresholding_supported(void) { - if (cpu_vendor_id != CPU_VENDOR_AMD) + if (cpu_vendor_id != CPU_VENDOR_AMD && + cpu_vendor_id != CPU_VENDOR_HYGON) return (false); /* * The RASCap register is wholly reserved in families 0x10-0x15 (through model 1F). Modified: stable/12/sys/x86/x86/mp_x86.c ============================================================================== --- stable/12/sys/x86/x86/mp_x86.c Tue Jan 28 11:29:06 2020 (r357199) +++ stable/12/sys/x86/x86/mp_x86.c Tue Jan 28 11:33:12 2020 (r357200) @@ -508,7 +508,8 @@ topo_probe(void) if (mp_ncpus <= 1) ; /* nothing */ - else if (cpu_vendor_id == CPU_VENDOR_AMD) + else if (cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_HYGON) topo_probe_amd(); else if (cpu_vendor_id == CPU_VENDOR_INTEL) topo_probe_intel(); Modified: stable/12/sys/x86/x86/msi.c ============================================================================== --- stable/12/sys/x86/x86/msi.c Tue Jan 28 11:29:06 2020 (r357199) +++ stable/12/sys/x86/x86/msi.c Tue Jan 28 11:33:12 2020 (r357200) @@ -319,6 +319,7 @@ msi_init(void) switch (cpu_vendor_id) { case CPU_VENDOR_INTEL: case CPU_VENDOR_AMD: + case CPU_VENDOR_HYGON: break; case CPU_VENDOR_CENTAUR: if (CPUID_TO_FAMILY(cpu_id) == 0x6 && Modified: stable/12/sys/x86/x86/tsc.c ============================================================================== --- stable/12/sys/x86/x86/tsc.c Tue Jan 28 11:29:06 2020 (r357199) +++ stable/12/sys/x86/x86/tsc.c Tue Jan 28 11:33:12 2020 (r357200) @@ -254,6 +254,7 @@ probe_tsc_freq(void) switch (cpu_vendor_id) { case CPU_VENDOR_AMD: + case CPU_VENDOR_HYGON: if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || (vm_guest == VM_GUEST_NO && CPUID_TO_FAMILY(cpu_id) >= 0x10)) @@ -517,6 +518,7 @@ retry: if (smp_tsc && tsc_is_invariant) { switch (cpu_vendor_id) { case CPU_VENDOR_AMD: + case CPU_VENDOR_HYGON: /* * Starting with Family 15h processors, TSC clock * source is in the north bridge. Check whether @@ -614,7 +616,8 @@ init: for (shift = 0; shift <= 31 && (tsc_freq >> shift) > max_freq; shift++) ; if ((cpu_feature & CPUID_SSE2) != 0 && mp_ncpus > 1) { - if (cpu_vendor_id == CPU_VENDOR_AMD) { + if (cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_HYGON) { tsc_timecounter.tc_get_timecount = shift > 0 ? tsc_get_timecount_low_mfence : tsc_get_timecount_mfence;
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