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Date:      Sat, 21 Mar 2015 06:05:11 -0600
From:      Warner Losh <imp@bsdimp.com>
To:        John Wehle <john@feith.com>
Cc:        freebsd-arm@freebsd.org, ian@freebsd.org
Subject:   Re: current meaning of BUS_DMA_COHERENT
Message-ID:  <B91C6F30-A0C8-4FB7-AD63-653ED34DBFB4@bsdimp.com>
In-Reply-To: <201503210131.t2L1VrAx012383@jwlab.FEITH.COM>
References:  <201503210131.t2L1VrAx012383@jwlab.FEITH.COM>

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> On Mar 20, 2015, at 7:31 PM, John Wehle <john@feith.com> wrote:
>=20
> On Mar 20, 2015, at 8:27 AM, Ian Lepore <ian@freebsd.org> wrote:
>> The main problem is shared concurrent-access memory, such as buffer
>> descriptor rings which are accessed simultaneously by the cpu and
>> network hardware.  (The same thing happens with other hardware, but =
NICs
>> are the prime example of it.)
>> ...
>> What we really need is a new type of busdma memory =
(BUS_DMA_DESCRIPTOR)
>> and a special sync call to use in conjunction with it that takes an
>> offset and length, and the sync is a single operation, no pre/post
>> stuff.
>=20
> If you have descriptor A being modified by the device at the same time
> descriptor B is modified by the CPU and they are in the same cache =
line
> you'll still have problems even with a sync call which takes an offset
> and length.
>=20
> Doesn't being able to sync individual descriptors also require padding =
the
> descriptor size so it's a multiple of the cache line size?

Only if you access them as coherent, cached memory. If you access them
as uncached memory, you don=E2=80=99t need to worry.

Warner


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