Date: Fri, 14 Apr 2023 19:10:15 GMT From: =?utf-8?Q?Stefan=20E=C3=9Fer?= <se@FreeBSD.org> To: ports-committers@FreeBSD.org, dev-commits-ports-all@FreeBSD.org, dev-commits-ports-main@FreeBSD.org Subject: git: c1c94249f573 - main - lang/silq: update to latest development version Message-ID: <202304141910.33EJAFng094545@gitrepo.freebsd.org>
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The branch main has been updated by se: URL: https://cgit.FreeBSD.org/ports/commit/?id=c1c94249f573aef6c4dd3aa3b88ddca51e364827 commit c1c94249f573aef6c4dd3aa3b88ddca51e364827 Author: Stefan Eßer <se@FreeBSD.org> AuthorDate: 2023-04-14 19:09:52 +0000 Commit: Stefan Eßer <se@FreeBSD.org> CommitDate: 2023-04-14 19:09:52 +0000 lang/silq: update to latest development version --- lang/silq/Makefile | 9 ++- lang/silq/distinfo | 14 ++--- lang/silq/pkg-plist | 160 +++++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 168 insertions(+), 15 deletions(-) diff --git a/lang/silq/Makefile b/lang/silq/Makefile index 2de04f04e682..081925050f23 100644 --- a/lang/silq/Makefile +++ b/lang/silq/Makefile @@ -1,6 +1,5 @@ PORTNAME= silq -PORTVERSION= 20220224 -PORTREVISION= 2 +PORTVERSION= 20230412 CATEGORIES= lang math science DIST_SUBDIR= silq @@ -19,9 +18,9 @@ BUILD_DEPENDS= ldmd2:lang/ldc \ USE_GITHUB= yes -GH_TUPLE= eth-sri:silq:afaf865 \ - tgehr:ast:d2f25fb:ast/ast \ - tgehr:util:7e9f0ce:util/util +GH_TUPLE= eth-sri:silq:e9750cb \ + tgehr:ast:072796e:ast/ast \ + tgehr:util:a4532a4:util/util OPTIONS_DEFINE= EXAMPLES diff --git a/lang/silq/distinfo b/lang/silq/distinfo index dd9943309d4e..1e64b52c4f42 100644 --- a/lang/silq/distinfo +++ b/lang/silq/distinfo @@ -1,7 +1,7 @@ -TIMESTAMP = 1650392986 -SHA256 (silq/eth-sri-silq-20220224-afaf865_GH0.tar.gz) = 37e8ad58f4ac0b60f510af188cc167e4e8ef767f949b60f66fd7c4b339d6dc8c -SIZE (silq/eth-sri-silq-20220224-afaf865_GH0.tar.gz) = 167609 -SHA256 (silq/tgehr-ast-d2f25fb_GH0.tar.gz) = bfec0dd622f726fd4a8d0e05967bcbb7578468c33d1295aa4d82bf540f459c83 -SIZE (silq/tgehr-ast-d2f25fb_GH0.tar.gz) = 75363 -SHA256 (silq/tgehr-util-7e9f0ce_GH0.tar.gz) = f73af612a6aa14c966cc46f392394d8c43b90ecf8c0be0c44b509cc07a7e949f -SIZE (silq/tgehr-util-7e9f0ce_GH0.tar.gz) = 9455 +TIMESTAMP = 1681284932 +SHA256 (silq/eth-sri-silq-20230412-e9750cb_GH0.tar.gz) = f6e201f4fb1e639f7d8df9e018dbf79bda6e8a55f431801385abf6070f37e01e +SIZE (silq/eth-sri-silq-20230412-e9750cb_GH0.tar.gz) = 187476 +SHA256 (silq/tgehr-ast-072796e_GH0.tar.gz) = ea5a472d6b2f7defbce624879abc9d5d87f3b3fb3ce5634172567e29b132567a +SIZE (silq/tgehr-ast-072796e_GH0.tar.gz) = 87630 +SHA256 (silq/tgehr-util-a4532a4_GH0.tar.gz) = 667a992d464e88a1aec85efc5718bf309786b62f2e120d02f3f5f20088e1d1ad +SIZE (silq/tgehr-util-a4532a4_GH0.tar.gz) = 9975 diff --git a/lang/silq/pkg-plist b/lang/silq/pkg-plist index c53355bd5b7b..f90cc49cdebd 100644 --- a/lang/silq/pkg-plist +++ b/lang/silq/pkg-plist @@ -1,18 +1,26 @@ bin/silq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/argMatchSubtyping1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/argMatchSubtyping2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/arrayAddAssign.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/arrayConcatReassign.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/arrayConsumeIndexReplace.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/arrayElements.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/arrayEntryDup.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/asinQ.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/asinQ2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/assertTypeError.slq -%%PORTEXAMPLES%%%%EXAMPLESDIR%%/assignError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/assignFromArray.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/assignQcontrol.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/assignQuantumArray.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badControlUncomp.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/badForget.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badForget2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/badIndexReplacement.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badIndexReplacement2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badProdType.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/badReverse.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badSliceReplacement.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badSliceReplacement2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/badTypes.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/bernsteinVazirani.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/bernsteinVazirani2.slq @@ -20,9 +28,25 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/bug.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/builtInToPrelude.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureConst.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureConsumes.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement4.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement5.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement6.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement7.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureShadow.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureTwice.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalArrayAliasing.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalAssign.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForget1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForget2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForget3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForget3_1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForget4.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForget5.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForgetBad.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalHadamard.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalQfree1.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalQfree2.slq @@ -91,8 +115,11 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/c2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/c3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/c3_2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/c3_3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d1.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d2_bad.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d2_todo.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d4.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d5.slq @@ -104,18 +131,28 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/warmup/u2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/warmup/u3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceAssign.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceBoolToInt.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceFunction.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceInt.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceIntLengthMismatch.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceIntToNat.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceIntToVecLengthMismatch.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceNegativeNatural.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceReal.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceTupleLengthMismatch.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceVecToIntLengthMismatch.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceVector.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceVectorLengthMismatch.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/communicationGame.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/concatJoin.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/condTwoAssertFalse.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/conditionalMeasurement.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/conditionalMeasurement2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/constBlockAssign.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/constBlockCapture.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/consumeAssign.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/consumeDepTypeVar.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/consumingSquare.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/consumingVector.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/conv.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/convertForget.slq @@ -125,13 +162,31 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/convertNatToInt.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/convertTuple.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/convertVectors.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depCond1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depCond2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depCond3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depCond4.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depConsume1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depConsume2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depConsume3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depIndexReplace.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depIndexReplace2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest4.slq -%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest5.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest5_1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest5_2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest5_3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest5_4.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest6.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/depType.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depType2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depType2_1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depType3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depType4.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/dependencyLoop1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/dependencyLoop2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/detectZero.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/distinguish0H0.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/distinguish0H0_2.slq @@ -164,6 +219,16 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/extendTruncateError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/fib.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/fib2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor10.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor4.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor5.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor6.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor7.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor8.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor9.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/flipAll.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/for.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/forStep.slq @@ -193,10 +258,12 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/functionBodyParseError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/genericAddition.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/genericReverse.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/genericSubtyping1.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/grover.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/grover2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/groverDiffusion.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/hIndex.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/hideAssign.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/hidingIndexReplacement.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ifError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ifFalseReassign.slq @@ -205,7 +272,15 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ifSuperposition3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/implicitDup.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/implicitDupLifted.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/inOwnType.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/incompatibleFunDef.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexAssignDep.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds10.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds11.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds12.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds13.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds14.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds4.slq @@ -214,7 +289,20 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds7.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds8.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds9.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplace1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplace2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplace3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplace4.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplace5.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplace6.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceAlias1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceConstAccess.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceConsume.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceError2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceErrorRhs.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceId.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceIfFunctionCall.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexRewriteContext.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/innerProduct.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/innerProduct2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/intUintBoolConversion.slq @@ -226,27 +314,49 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ite2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ite3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ite4.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ite5.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ite6.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/iteLhs.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/iteLhs2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/iverson.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/lambdaEq.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/lambdaLhs.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/lengthConstFold.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/lengthMismatch.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/liftedAssign.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/liftedConstArg.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/localVariableInFunctionReturnTypeError.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/logicShortCircuit.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/loopFixedPoint1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/loopFixedPoint2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/loopFixedPoint3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/loopFixedPoint4.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/loopFixedPoint5.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/loopFixedPoint6.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/majorityOracle.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/makeWPower2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/map1.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/map2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/map3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mapH.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mapH2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mapH3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/matchCoerce.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureArray.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureFun.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureFun2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureHadamard.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureReversePhase.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureUint.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureVector.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mergeImplicitForget.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/mfreeImplicitForget.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/mixed.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/mixed2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/mixed3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/mixed4.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/mixed5.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiDimReplace.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiForget.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiIndex1.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiIndex2.slq @@ -254,12 +364,18 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiReplace.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiResultIndexReplace.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/mustConsumeNonLifted.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestInf.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedCapture.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedClosure.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedGlobal.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedIndexReplace.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedMeasure.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedReplace.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedTupleMatch.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/newForLoopRangeSyntax.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/noImplicitForget.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/noLengthAssign.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/noQnumericJoin.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/opAssignReverse.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/paramNotConsumedError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/parameterizedSimulation.slq @@ -287,9 +403,16 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/print.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/qft.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/qftPretty.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/qnumeric1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/qnumericError1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/qnumericError2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/qnumericError3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumBitNotMinus.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumControlClassicalAssignment.slq -%%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumIfClassicalUpdate.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumIfClassicalUpdate1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumIfClassicalUpdate2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumIfClassicalUpdate3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumReplace.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/quid-updates.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/rationalPhase.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reassignArrayLength.slq @@ -302,6 +425,7 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/repeat.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/repeat100.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/repeatUntil.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceClassical.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndex.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti0.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti1.slq @@ -311,13 +435,16 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti5.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti6.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti7.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti8.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ret2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/retClosure.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/retPi.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reuseCapturedName.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseArithmetic.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseDependent.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseEarlyReturn.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseFlatten.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseGeneric.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseH.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseH0.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseH2.slq @@ -335,9 +462,15 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseRotX.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseRotY.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseRotZ.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSingletonArg.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare1.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare4.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare5.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare6.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare7.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSubtype.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseToW.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseX.slq @@ -346,8 +479,18 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/shor.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/sinQ.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/singletonVectorHadamard.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/sliceReplacement.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/specialReverseTypeChecking.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/splitArrayConst.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/squareFunctionLhs.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/squareFunctionLhsConst.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/squareFunctionLhsConst2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/squareFunctionLhsConst3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/squareFunctionReplace.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/strongUpdates1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/strongUpdates2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/subAssign1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/subAssign2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/subtyping.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/sumArray.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/sumIota.slq @@ -355,10 +498,12 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapArray2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapArray3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapArray4.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapArray5.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapClosures.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapDiffArrays.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapEmptyIf.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapInt.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapNoSwap.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapVarWithComponent.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapVarWithComponent2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/teleportation.slq @@ -393,20 +538,29 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/testUnsafeCaptureConst2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/testUnsafeCaptureConst3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/testUnsafeCaptureConst4.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/tf.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/tf_orig.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/thirds.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/transpose.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/tupleArray.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/tupleComp.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/tupleConversion.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeAlias.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeConstBlockCapture.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeConstBlockForget.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeError2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeFunCall.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeFunCallCoerce.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/uncomputeOnArrayAssignment.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/undefLhs.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/unicodeLoc.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/unitParamClosureArray.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/unitRedefinition.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/unrealizableError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/vectorConv.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/vectorLength.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/vectorReverse.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/vectorToArray.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/warning.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/while.slq
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