From owner-svn-src-head@FreeBSD.ORG Fri Mar 26 07:15:27 2010 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 9EB57106566B; Fri, 26 Mar 2010 07:15:27 +0000 (UTC) (envelope-from neel@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 8C3EC8FC08; Fri, 26 Mar 2010 07:15:27 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o2Q7FRKA073906; Fri, 26 Mar 2010 07:15:27 GMT (envelope-from neel@svn.freebsd.org) Received: (from neel@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o2Q7FRFn073901; Fri, 26 Mar 2010 07:15:27 GMT (envelope-from neel@svn.freebsd.org) Message-Id: <201003260715.o2Q7FRFn073901@svn.freebsd.org> From: Neel Natu Date: Fri, 26 Mar 2010 07:15:27 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r205675 - in head/sys/mips: include mips sibyte X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 26 Mar 2010 07:15:27 -0000 Author: neel Date: Fri Mar 26 07:15:27 2010 New Revision: 205675 URL: http://svn.freebsd.org/changeset/base/205675 Log: Replace sb_store64()/sb_load64() with mips3_sd()/mips3_ld() respectively. Obtained from NetBSD. Suggested by: jmallett@ Modified: head/sys/mips/include/cpufunc.h head/sys/mips/mips/support.S head/sys/mips/sibyte/sb_asm.S head/sys/mips/sibyte/sb_scd.c Modified: head/sys/mips/include/cpufunc.h ============================================================================== --- head/sys/mips/include/cpufunc.h Fri Mar 26 06:06:20 2010 (r205674) +++ head/sys/mips/include/cpufunc.h Fri Mar 26 07:15:27 2010 (r205675) @@ -283,6 +283,35 @@ breakpoint(void) __asm __volatile ("break"); } +#if defined(__GNUC__) && !defined(__mips_o32) +static inline uint64_t +mips3_ld(const volatile uint64_t *va) +{ + uint64_t rv; + +#if defined(_LP64) + rv = *va; +#else + __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); +#endif + + return (rv); +} + +static inline void +mips3_sd(volatile uint64_t *va, uint64_t v) +{ +#if defined(_LP64) + *va = v; +#else + __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); +#endif +} +#else +uint64_t mips3_ld(volatile uint64_t *va); +void mips3_sd(volatile uint64_t *, uint64_t); +#endif /* __GNUC__ */ + #endif /* _KERNEL */ #define readb(va) (*(volatile uint8_t *) (va)) Modified: head/sys/mips/mips/support.S ============================================================================== --- head/sys/mips/mips/support.S Fri Mar 26 06:06:20 2010 (r205674) +++ head/sys/mips/mips/support.S Fri Mar 26 07:15:27 2010 (r205675) @@ -51,6 +51,38 @@ */ /* + * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Jonathan R. Stone for + * the NetBSD Project. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* * Contains code that is the first executed at boot time plus * assembly language support routines. */ @@ -61,6 +93,7 @@ #include #include #include +#include #include "assym.s" @@ -1586,3 +1619,78 @@ LEAF(octeon_get_control) .set mips0 END(octeon_get_control) #endif + +LEAF(mips3_ld) + .set push + .set noreorder + .set mips64 +#if defined(__mips_o32) + mfc0 t0, MIPS_COP_0_STATUS # turn off interrupts + and t1, t0, ~(MIPS_SR_INT_IE) + mtc0 t1, MIPS_COP_0_STATUS + COP0_SYNC + nop + nop + nop + + ld v0, 0(a0) +#if _BYTE_ORDER == _BIG_ENDIAN + dsll v1, v0, 32 + dsra v1, v1, 32 # low word in v1 + dsra v0, v0, 32 # high word in v0 +#else + dsra v1, v0, 32 # high word in v1 + dsll v0, v0, 32 + dsra v0, v0, 32 # low word in v0 +#endif + + mtc0 t0, MIPS_COP_0_STATUS # restore intr status. + COP0_SYNC + nop +#else /* !__mips_o32 */ + ld v0, 0(a0) +#endif /* !__mips_o32 */ + + jr ra + nop + .set pop +END(mips3_ld) + +LEAF(mips3_sd) + .set push + .set mips64 + .set noreorder +#if defined(__mips_o32) + mfc0 t0, MIPS_COP_0_STATUS # turn off interrupts + and t1, t0, ~(MIPS_SR_INT_IE) + mtc0 t1, MIPS_COP_0_STATUS + COP0_SYNC + nop + nop + nop + + # NOTE: a1 is padding! + +#if _BYTE_ORDER == _BIG_ENDIAN + dsll a2, a2, 32 # high word in a2 + dsll a3, a3, 32 # low word in a3 + dsrl a3, a3, 32 +#else + dsll a2, a2, 32 # low word in a2 + dsrl a2, a2, 32 + dsll a3, a3, 32 # high word in a3 +#endif + or a1, a2, a3 + sd a1, 0(a0) + + mtc0 t0, MIPS_COP_0_STATUS # restore intr status. + COP0_SYNC + nop +#else /* !__mips_o32 */ + sd a1, 0(a0) +#endif /* !__mips_o32 */ + + jr ra + nop + .set pop +END(mips3_sd) Modified: head/sys/mips/sibyte/sb_asm.S ============================================================================== --- head/sys/mips/sibyte/sb_asm.S Fri Mar 26 06:06:20 2010 (r205674) +++ head/sys/mips/sibyte/sb_asm.S Fri Mar 26 07:15:27 2010 (r205675) @@ -28,61 +28,11 @@ #include #include -#include - -/* - * We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit - * processor. It has some registers that must be accessed using 64-bit load - * and store instructions. - * - * So we have to resort to assembly because the compiler does not emit the - * 'ld' and 'sd' instructions since it thinks that it is compiling for a - * 32-bit mips processor. - */ .set mips64 .set noat .set noreorder -/* - * Parameters: uint32_t ptr - * Return value: *(uint64_t *)ptr - */ -LEAF(sb_load64) - ld v1, 0(a0) /* result = *(uint64_t *)ptr */ - move v0, v1 -#if _BYTE_ORDER == _BIG_ENDIAN - dsll32 v1, v1, 0 - dsra32 v1, v1, 0 /* v1 = lower_uint32(result) */ - jr ra - dsra32 v0, v0, 0 /* v0 = upper_uint32(result) */ -#else - dsll32 v0, v0, 0 - dsra32 v0, v0, 0 /* v0 = lower_uint32(result) */ - jr ra - dsra32 v1, v1, 0 /* v1 = upper_uint32(result) */ -#endif -END(sb_load64) - -/* - * Parameters: uint32_t ptr, uint64_t val - * Return value: void - */ -LEAF(sb_store64) -#if _BYTE_ORDER == _BIG_ENDIAN - dsll32 a2, a2, 0 /* a2 = upper_uint32(val) */ - dsll32 a3, a3, 0 /* a3 = lower_uint32(val) */ - dsrl32 a3, a3, 0 -#else - dsll32 a3, a3, 0 /* a3 = upper_uint32(val) */ - dsll32 a2, a2, 0 /* a2 = lower_uint32(val) */ - dsrl32 a2, a2, 0 -#endif - or t0, a2, a3 - jr ra - sd t0, 0(a0) -END(sb_store64) - #ifdef SMP /* * This function must be implemented in assembly because it is called early Modified: head/sys/mips/sibyte/sb_scd.c ============================================================================== --- head/sys/mips/sibyte/sb_scd.c Fri Mar 26 06:06:20 2010 (r205674) +++ head/sys/mips/sibyte/sb_scd.c Fri Mar 26 07:15:27 2010 (r205675) @@ -38,8 +38,15 @@ __FBSDID("$FreeBSD$"); #include "sb_scd.h" -extern void sb_store64(uint32_t addr, uint64_t val); -extern uint64_t sb_load64(uint32_t addr); +/* + * We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit + * processor. It has some registers that must be accessed using 64-bit load + * and store instructions. + * + * We use the mips_ld() and mips_sd() functions to do this for us. + */ +#define sb_store64(addr, val) mips3_sd((uint64_t *)(addr), (val)) +#define sb_load64(addr) mips3_ld((uint64_t *)(addr)) /* * System Control and Debug (SCD) unit on the Sibyte ZBbus.