From owner-freebsd-net@FreeBSD.ORG Sun Jan 3 13:55:22 2010 Return-Path: Delivered-To: freebsd-net@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id CA4F1106566B for ; Sun, 3 Jan 2010 13:55:22 +0000 (UTC) (envelope-from Michael.Tuexen@lurchi.franken.de) Received: from mail-n.franken.de (drew.ipv6.franken.de [IPv6:2001:638:a02:a001:20e:cff:fe4a:feaa]) by mx1.freebsd.org (Postfix) with ESMTP id 1E4C88FC0C for ; Sun, 3 Jan 2010 13:55:22 +0000 (UTC) Received: from [192.168.1.190] (p508FE5E5.dip.t-dialin.net [80.143.229.229]) by mail-n.franken.de (Postfix) with ESMTP id 7E2D91C0C0BC5; Sun, 3 Jan 2010 14:55:19 +0100 (CET) Mime-Version: 1.0 (Apple Message framework v1077) Content-Type: text/plain; charset=us-ascii From: =?iso-8859-1?Q?Michael_T=FCxen?= In-Reply-To: <969646.48748.qm@web63905.mail.re1.yahoo.com> Date: Sun, 3 Jan 2010 14:55:18 +0100 Content-Transfer-Encoding: quoted-printable Message-Id: References: <969646.48748.qm@web63905.mail.re1.yahoo.com> To: Barney Cordoba X-Mailer: Apple Mail (2.1077) Cc: freebsd-net@freebsd.org, jfvogel@gmail.com Subject: Re: igb interrupt moderation X-BeenThere: freebsd-net@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Networking and TCP/IP with FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 03 Jan 2010 13:55:23 -0000 Hi Barney, Hi Jack, some comments and some more questions inside... Best regards Michael On Jan 2, 2010, at 8:42 PM, Barney Cordoba wrote: > Jack, >=20 > I'm trying to get some clarification on differences I'm finding = between > the 82575 and 82576 parts with respect to interrupt moderation. The = spec > I have for the 82576 (82576_Datasheet_v2p1.pdf) indicates that the=20 I'm only commenting 82576. You can get rev 2.41 from intels website... >=20 > ITR algorithm is different than the one used (I don't have one of the > secret copies of the 82575 spec). The algorithm shown is >=20 > interrupts/sec =3D 1/(2 * 10-6sec x interval) (page 295, Section = 7.3.4) >=20 > which is clearly wrong from practice. I have an 82576 (device id 10C9) If you look at section 8.8.12, you find other formulas... Jack: Which ones are correct? > if I use the 125d setting in the example get just under 32000 = interrupts > per second. Clearly your code doesnt implement this, nor do you have > different settings for the 82575 and 82576 parts. So I assume that the=20= > same formula for the em parts hold for the igb parts, and that the=20 > datasheet is wrong? >=20 > There does seem to be a slight difference. The setting that gets 1000 > ints/second on the 82575 generates about 1020 on the 82576. Not a big > deal but I wonder why there's a difference? Is the reference clock for > these something that may not be fixed and could vary from board to=20 > board? Note that both devices are on the same MB. >=20 > Also, it seems that settings to EITR over 32767 wrap on the 82576 (for > example writing 32768 to EITR is the same as writing a 1). So the = minimum setting on the 82576 is around 125 ints/second. The 82575 can = accept=20 > values up the 65535 before wrapping.=20 Hmm, looking at the table in 8.8.12 would suggest: Setting it to one sets a reserved bit, but does not change the interval. Setting it to 2^15 should set the LLI_EN bit, but does not change in = interval. Jack is setting the register to igb_low_latency: 128 igb_ave_latency: 450 igb_bulk_latency: 1200 This would result in intervals of: igb_low_latency: 32 igb_ave_latency: 112 igb_bulk_latency: 300 Jack: What are the corresponding interrupt rates? The spec provides = different formulas and talks about a 1us, 2us or 8us counter. Not sure what = is right... Jack: Why are you setting bit1 (which is reserved) in the case = igb_ave_latency? And another question for Jack: In igb_update_aim() you do if (olditr !=3D newitr) { /* Change interrupt rate */ rxr->eitr_setting =3D newitr; E1000_WRITE_REG(&adapter->hw, E1000_EITR(rxr->me), newitr | (newitr << 16)); } So why are setting the higher bits of the EITR? You are setting igb_low_latency: the LL Counter becomes 0, the moderation counter = becomes 16 igb_ave_latency: the LL Counter becomes 2, the moderation counter = becomes 56 igb_bulk_latency: the LL Counter becomes 16, the moderation counter = becomes 148 I really do not understand these settings. Maybe the spec is wrong? Or = you do mean if (olditr !=3D newitr) { /* Change interrupt rate */ rxr->eitr_setting =3D newitr; E1000_WRITE_REG(&adapter->hw, E1000_EITR(rxr->me), = newitr); } Or do you want to preserve the counters, set the CNT_INGR bit and mean if (olditr !=3D newitr) { /* Change interrupt rate */ rxr->eitr_setting =3D newitr; E1000_WRITE_REG(&adapter->hw, E1000_EITR(rxr->me), = 0x80000000 | newitr); } Could you clarify that? >=20 > The 82576 document doesn't have a map of the register that I can find, = so > Im curious as to whether these observations are something I can assume = is > true across all parts and motherboards/cards, or is there some > implementation variance that will cause these to only apply to the = ones > I happen to be testing? >=20 > Thanks, >=20 > Barney >=20 >=20 >=20 >=20 > _______________________________________________ > freebsd-net@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-net > To unsubscribe, send any mail to "freebsd-net-unsubscribe@freebsd.org" >=20