From owner-freebsd-mips@FreeBSD.ORG Sun Nov 4 23:55:03 2012 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id E58E66E2 for ; Sun, 4 Nov 2012 23:55:03 +0000 (UTC) (envelope-from juli@clockworksquid.com) Received: from mail-ye0-f182.google.com (mail-ye0-f182.google.com [209.85.213.182]) by mx1.freebsd.org (Postfix) with ESMTP id 9CCD58FC0A for ; Sun, 4 Nov 2012 23:55:03 +0000 (UTC) Received: by mail-ye0-f182.google.com with SMTP id l8so968909yen.13 for ; Sun, 04 Nov 2012 15:55:02 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:from:date:message-id:subject:to:content-type :x-gm-message-state; bh=bMJCDwbV57BiLwXTZZxEr/gTUF+sBOKaWST45Q2A4Kk=; b=gwRIeiKzxuYnusBz8Dj0Job4F+7ghAXg/shqC7vrvkAevpRwh+wLNqE/nAMqarcjvZ AscmWQjoXUoAiOfmdHMcAQqpKtccoqE4soHwt5nG++6u+VTtt5fMCzA6cy53SJdnJ7Kx EQKzRSEe9C9B0jXvrTTrW8ndQ2IiU0retqBYC3hEFFj1SDe5QnINfoCcUIzniQ8lK7X+ pXyDoTAcmO0Lbmii9v5jgkXpNB9Pfj+4MPl/Voi6H2nT1MRqhMbo5UeBYYKCYYw2+eBM QNPYTjJbq5Jt78cQP9TkOWbOPVfwq622YWl6J5sJwNg3i8dBeFlGAYCIug6rsvA6Kmoc ePWg== Received: by 10.236.131.138 with SMTP id m10mr7474705yhi.101.1352073302793; Sun, 04 Nov 2012 15:55:02 -0800 (PST) MIME-Version: 1.0 Received: by 10.146.227.39 with HTTP; Sun, 4 Nov 2012 15:54:42 -0800 (PST) From: Juli Mallett Date: Sun, 4 Nov 2012 15:54:42 -0800 Message-ID: Subject: CACHE_LINE_SIZE macro. To: "freebsd-mips@FreeBSD.org" X-Gm-Message-State: ALoCoQkvgUCRqFWsCugvTT/QpDgGlg/lhpbJ32hEyfuklz3VEfoE1Ur7+f+xUULTX+AWS3YtwZZD Content-Type: text/plain; charset=UTF-8 X-Content-Filtered-By: Mailman/MimeDel 2.1.14 X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 04 Nov 2012 23:55:04 -0000 Fellow FreeBSD/MIPSists, CACHE_LINE_SIZE is being used increasingly-much in ways which may have ABI implications, etc. It is currentyl 2^6, whereas at least the Cavium Octeon has cache lines that are actually 2^7 bytes in size. It would be nice to expose the correct value to reduce false line sharing, etc., but making it dependent on the CPU type raises ABI issues, as well as questions about how to reliably get the right value to userland. It seems to me that increasing it to 2^7 is the most viable approach, but I can imagine there might be some concerns about that, so I wanted to run it past this list first. Questions, comments, concerns? Are there MIPS CPUs with 2^8-byte or larger cache lines that we support or will support or which are likely coming over the horizon? Thanks, Juli.