From owner-freebsd-smp Mon Jun 29 23:14:12 1998 Return-Path: Received: (from majordom@localhost) by hub.freebsd.org (8.8.8/8.8.8) id XAA08931 for freebsd-smp-outgoing; Mon, 29 Jun 1998 23:14:12 -0700 (PDT) (envelope-from owner-freebsd-smp@FreeBSD.ORG) Received: from panzer.plutotech.com (ken@panzer.plutotech.com [206.168.67.125]) by hub.freebsd.org (8.8.8/8.8.8) with ESMTP id XAA08869; Mon, 29 Jun 1998 23:14:03 -0700 (PDT) (envelope-from ken@panzer.plutotech.com) Received: (from ken@localhost) by panzer.plutotech.com (8.8.8/8.8.5) id AAA26408; Tue, 30 Jun 1998 00:13:56 -0600 (MDT) From: "Kenneth D. Merry" Message-Id: <199806300613.AAA26408@panzer.plutotech.com> Subject: Re: Intel announces Xeon!!! Was Re: PPro vs PII In-Reply-To: from Atipa at "Jun 29, 98 08:47:20 pm" To: freebsd@atipa.com (Atipa) Date: Tue, 30 Jun 1998 00:13:56 -0600 (MDT) Cc: leo@talcom.net, freebsd-smp@FreeBSD.ORG, sos@FreeBSD.ORG X-Mailer: ELM [version 2.4ME+ PL28s (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: owner-freebsd-smp@FreeBSD.ORG Precedence: bulk X-Loop: FreeBSD.org Atipa wrote... > > This thread is now obselete, since the new Xeon has the best features of > both chips. > > Features Comment > ------------------- -------------------- > 400Mhz CPU Fast as fastest P2 > 400MHz cache 1:1 caching (like PPro) > DIB Dual Independent Bus (from P2; double bandwidth) > 1MB L2 cache From PPro. > 36-bit memory Supports over 64GB RAM cached (best yet) Although the 450NX chipset only support 8GB DRAM. The interesting thing is, the chipset supports 36-bit addressing. > 8-way SMP capable Better than both (w/o weird chipsets) Well, the Xeon itself only has "native" support for 4-way SMP. (despite what Intel's product brief says: http://developer.intel.com/design/pentiumii/xeon/prodbref/ Their data sheet for the Xeon: http://developer.intel.com/design/pentiumii/xeon/datashts/243770.htm indicates that it only has "native" support for 4-way SMP. To do otherwise would require changing the P6 processor bus, which they haven't done.) The 450NX chipset apparantly has provision for connecting a 3rd party "cluster bridge" to the system bus and the "MIOC" (memory and I/O controller). The thing they say is that the 3rd party cluster bridge would operate at "reduced frequencies". (see: http://developer.intel.com/design/pcisets/450nx/index.htm) Their "and beyond" statement on that page leads me to believe that you could probably have a cluster bridge that connects more than two P6 busses. For instance, you could have 8 groups of 450NX chipsets, each with 4 Xeon processors and 8GB of RAM, all connected by third-party processor bus bridges. Since the chips and the chipsets all support 36-bit addressing, you would be able to address all 64GB of memory from any one of the 32 processors. Sounds neat. > "Cluster Support" Can cluster 4 servers? Ask Intel on that... I think the "cluster support" refers to clusters of Xeon processors connected by processor bus bridge chips, like Corollary supposedly makes. I think Intel bought them. Axil (http://www.axil.com) already makes 8-way systems. But I think they've been pretty much shut down. See: http://www.eet.com/news/98/1014news/cuts.html Ken -- Kenneth Merry ken@plutotech.com To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-smp" in the body of the message