From owner-svn-soc-all@FreeBSD.ORG Sat Aug 18 16:50:15 2012 Return-Path: Delivered-To: svn-soc-all@FreeBSD.org Received: from socsvn.FreeBSD.org (unknown [IPv6:2001:4f8:fff6::2f]) by hub.freebsd.org (Postfix) with SMTP id 0D9761065670 for ; Sat, 18 Aug 2012 16:50:13 +0000 (UTC) (envelope-from aleek@FreeBSD.org) Received: by socsvn.FreeBSD.org (sSMTP sendmail emulation); Sat, 18 Aug 2012 16:50:13 +0000 Date: Sat, 18 Aug 2012 16:50:13 +0000 From: aleek@FreeBSD.org To: svn-soc-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-Id: <20120818165013.0D9761065670@hub.freebsd.org> Cc: Subject: socsvn commit: r240496 - in soc2012/aleek/beaglexm-armv6/sys: arm/conf arm/ti/twl arm/ti/usb boot/fdt/dts X-BeenThere: svn-soc-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the entire Summer of Code repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 18 Aug 2012 16:50:15 -0000 Author: aleek Date: Sat Aug 18 16:50:12 2012 New Revision: 240496 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=240496 Log: fixing the TWL VREG module Modified: soc2012/aleek/beaglexm-armv6/sys/arm/conf/BEAGLEBOARD-XM soc2012/aleek/beaglexm-armv6/sys/arm/ti/twl/twl_vreg.c soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_ehci.c soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_usb.h soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts Modified: soc2012/aleek/beaglexm-armv6/sys/arm/conf/BEAGLEBOARD-XM ============================================================================== --- soc2012/aleek/beaglexm-armv6/sys/arm/conf/BEAGLEBOARD-XM Sat Aug 18 14:05:16 2012 (r240495) +++ soc2012/aleek/beaglexm-armv6/sys/arm/conf/BEAGLEBOARD-XM Sat Aug 18 16:50:12 2012 (r240496) @@ -60,7 +60,7 @@ #options WITNESS #Enable checks to detect deadlocks and cycles #options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed #options DIAGNOSTIC -options DEBUG +#options DEBUG # MMC/SD/SDIO card slot support Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/twl/twl_vreg.c ============================================================================== --- soc2012/aleek/beaglexm-armv6/sys/arm/ti/twl/twl_vreg.c Sat Aug 18 14:05:16 2012 (r240495) +++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/twl/twl_vreg.c Sat Aug 18 16:50:12 2012 (r240496) @@ -90,6 +90,7 @@ * Register offsets within a LDO regulator register set */ #define TWL_VREG_GRP 0x00 /* Regulator GRP register */ +#define TWL_VREG_TYPE 0x01 #define TWL_VREG_STATE 0x02 #define TWL_VREG_VSEL 0x03 /* Voltage select register */ @@ -169,22 +170,22 @@ { name, subdev, reg, voltage, NULL, 0 } static const struct twl_regulator twl4030_regulators[] = { - TWL_REGULATOR_ADJUSTABLE("vaux1", 0, 0x17, twl4030_vaux1_voltages), - TWL_REGULATOR_ADJUSTABLE("vaux2", 0, 0x1B, twl4030_vaux2_voltages), - TWL_REGULATOR_ADJUSTABLE("vaux3", 0, 0x1F, twl4030_vaux3_voltages), - TWL_REGULATOR_ADJUSTABLE("vaux4", 0, 0x23, twl4030_vaux4_voltages), - TWL_REGULATOR_ADJUSTABLE("vmmc1", 0, 0x27, twl4030_vmmc1_voltages), - TWL_REGULATOR_ADJUSTABLE("vmmc2", 0, 0x2B, twl4030_vmmc2_voltages), - TWL_REGULATOR_ADJUSTABLE("vpll1", 0, 0x2F, twl4030_vpll1_voltages), - TWL_REGULATOR_ADJUSTABLE("vpll2", 0, 0x33, twl4030_vpll2_voltages), - TWL_REGULATOR_ADJUSTABLE("vsim", 0, 0x37, twl4030_vsim_voltages), - TWL_REGULATOR_ADJUSTABLE("vdac", 0, 0x3B, twl4030_vdac_voltages), - TWL_REGULATOR_ADJUSTABLE("vintana2", 0, 0x43, twl4030_vintana2_voltages), - TWL_REGULATOR_FIXED("vintana1", 0, 0x3F, 1500), - TWL_REGULATOR_FIXED("vintdig", 0, 0x47, 1500), - TWL_REGULATOR_FIXED("vusb1v5", 0, 0x71, 1500), - TWL_REGULATOR_FIXED("vusb1v8", 0, 0x74, 1800), - TWL_REGULATOR_FIXED("vusb3v1", 0, 0x77, 3100), + TWL_REGULATOR_ADJUSTABLE("vaux1", 3, 0x72, twl4030_vaux1_voltages), + TWL_REGULATOR_ADJUSTABLE("vaux2", 3, 0x76, twl4030_vaux2_voltages), + TWL_REGULATOR_ADJUSTABLE("vaux3", 3, 0x7A, twl4030_vaux3_voltages), + TWL_REGULATOR_ADJUSTABLE("vaux4", 3, 0x7E, twl4030_vaux4_voltages), + TWL_REGULATOR_ADJUSTABLE("vmmc1", 3, 0x82, twl4030_vmmc1_voltages), + TWL_REGULATOR_ADJUSTABLE("vmmc2", 3, 0x86, twl4030_vmmc2_voltages), + TWL_REGULATOR_ADJUSTABLE("vpll1", 0, 0x8A, twl4030_vpll1_voltages), + TWL_REGULATOR_ADJUSTABLE("vpll2", 0, 0x8E, twl4030_vpll2_voltages), + TWL_REGULATOR_ADJUSTABLE("vsim", 0, 0x92, twl4030_vsim_voltages), + TWL_REGULATOR_ADJUSTABLE("vdac", 0, 0x96, twl4030_vdac_voltages), + TWL_REGULATOR_ADJUSTABLE("vintana2", 0, 0x9E, twl4030_vintana2_voltages), + TWL_REGULATOR_FIXED("vintana1", 3, 0x92, 1500), + TWL_REGULATOR_FIXED("vintdig", 3, 0xA2, 1500), + TWL_REGULATOR_FIXED("vusb1v5", 3, 0xCC, 1500), + TWL_REGULATOR_FIXED("vusb1v8", 3, 0xCF, 1800), + TWL_REGULATOR_FIXED("vusb3v1", 3, 0xD2, 3100), { NULL, 0, 0x00, 0, NULL, 0 } }; @@ -512,8 +513,9 @@ err = twl_vreg_read_1(sc, regulator, TWL_VREG_GRP, &grp); - if (err) + if (err){ goto done; + } /* Enable the regulator by ensuring it's in the application power group * and is in the "on" state. @@ -525,6 +527,8 @@ */ grp |= TWL4030_P1_GRP; err = twl_vreg_write_1(sc, regulator, TWL_VREG_GRP, grp); + twl_vreg_write_1(sc, regulator, TWL_VREG_TYPE, 0x00); + } else if (twl_is_6030(sc->sc_pdev) || twl_is_6025(sc->sc_pdev)) { @@ -570,11 +574,14 @@ uint8_t vsel; int xlocked; + TWL_VREG_ASSERT_LOCKED(sc); /* If millivolts is zero then we simply disable the output */ if (millivolts == 0) + { return (twl_vreg_disable_regulator(sc, regulator)); + } /* If the regulator has a fixed voltage then check the setting matches * and simply enable. @@ -597,7 +604,6 @@ if (!xlocked) TWL_VREG_LOCK_UPGRADE(sc); - /* Set voltage and enable (atomically) */ err = twl_vreg_write_1(sc, regulator, TWL_VREG_VSEL, (vsel & 0x1f)); if (!err) { @@ -607,11 +613,11 @@ if (!xlocked) TWL_VREG_LOCK_DOWNGRADE(sc); -#ifdef DEBUG +//#ifdef DEBUG if (!err) device_printf(sc->sc_dev, "%s : setting voltage to %dmV (vsel: 0x%x)\n", regulator->name, millivolts, vsel); -#endif +//#endif return (err); } @@ -689,11 +695,11 @@ if (!xlocked) TWL_VREG_LOCK_DOWNGRADE(sc); -#ifdef DEBUG +//#ifdef DEBUG if (!err) device_printf(sc->sc_dev, "%s : reading voltage is %dmV (vsel: 0x%x)\n", regulator->name, *millivolts, vsel); -#endif +//#endif return (err); } @@ -897,7 +903,6 @@ twl_vreg_add_regulators(struct twl_vreg_softc *sc, const struct twl_regulator *regulators) { - int err; int millivolts; const struct twl_regulator *walker; struct twl_regulator_entry *entry; @@ -905,6 +910,15 @@ char rnames[256]; char *name, *voltage; int len = 0, prop_len; + uint8_t val; + + /* Enable writing to power configuration registers */ + if (twl_is_4030(sc->sc_pdev)) { + val = 0xC0; + twl_write( sc->sc_pdev, 3, 0x44, &val, 1 ); + val = 0x0C; + twl_write( sc->sc_pdev, 3, 0x44, &val, 1 ); + } /* Add the regulators from the list */ @@ -942,20 +956,24 @@ LIST_FOREACH(entry, &sc->sc_vreg_list, entries) { if (strcmp(entry->name, name) == 0) { device_printf( sc->sc_dev, "Setting %s voltage to %d\n", entry->name, millivolts ); - twl_vreg_write_regulator_voltage(sc, entry, millivolts); + if( twl_vreg_write_regulator_voltage(sc, entry, millivolts) != 0 ) + { + device_printf( sc->sc_dev, "Falied setting %s voltage to %d\n", entry->name, millivolts ); + } break; } } } } -#ifdef DEBUG +//#ifdef DEBUG + int err; LIST_FOREACH(entry, &sc->sc_vreg_list, entries) { err = twl_vreg_read_regulator_voltage(sc, entry, &millivolts); if (!err) device_printf(sc->sc_dev, "%s : %d mV\n", entry->name, millivolts); } -#endif +//#endif return (0); } Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_ehci.c ============================================================================== --- soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_ehci.c Sat Aug 18 14:05:16 2012 (r240495) +++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_ehci.c Sat Aug 18 16:50:12 2012 (r240496) @@ -102,9 +102,6 @@ #include #include -#include -#include - #include #include "gpio_if.h" @@ -114,7 +111,6 @@ device_t sc_dev; device_t sc_gpio_dev; - device_t sc_vreg_dev; /* TLL register set */ struct resource* tll_mem_res; @@ -312,13 +308,13 @@ omap_ehci_write_4(isc, OMAP_USBHOST_INSNREG05_ULPI, reg); - device_printf(isc->sc_dev, "Waiting for phy reset operation\n"); /* Wait for ULPI access completion */ while ((omap_ehci_read_4(isc, OMAP_USBHOST_INSNREG05_ULPI) & (1 << OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT))) { /* Sleep for a tick */ pause("USBPHY_RESET", 1); + if (timeout-- == 0) { device_printf(isc->sc_dev, "PHY reset operation timed out\n"); break; @@ -350,35 +346,9 @@ uint32_t reg = 0; int reset_performed = 0; int i; - //int milivolts; device_printf(isc->sc_dev, "Starting TI EHCI USB Controller\n"); - device_printf( isc->sc_dev, "INSNREG05: 0x%08x\n", omap_ehci_read_4(isc, OMAP_USBHOST_INSNREG05_ULPI ) ); -#if 0 - if( twl_vreg_get_voltage(isc->sc_vreg_dev, "vusb1v5", &milivolts) != 0) - { - device_printf(isc->sc_dev, "dupa!\n"); - //return EINVAL; - } - device_printf( isc->sc_dev, "vusb1v5: %d\n", milivolts ); - twl_vreg_get_voltage(isc->sc_vreg_dev, "vusb1v8", &milivolts); - device_printf( isc->sc_dev, "vusb1v8: %d\n", milivolts ); - twl_vreg_get_voltage(isc->sc_vreg_dev, "vusb3v1", &milivolts); - device_printf( isc->sc_dev, "vusb1v8: %d\n", milivolts ); - - twl_vreg_set_voltage(isc->sc_vreg_dev, "vusb1v5", 1500); - twl_vreg_set_voltage(isc->sc_vreg_dev, "vusb1v8", 1800); - twl_vreg_set_voltage(isc->sc_vreg_dev, "vusb3v1", 3100); - device_printf( isc->sc_dev, "INSNREG05: 0x%08x\n", omap_ehci_read_4(isc, OMAP_USBHOST_INSNREG05_ULPI ) ); - twl_vreg_get_voltage(isc->sc_vreg_dev, "vusb1v5", &milivolts); - device_printf( isc->sc_dev, "vusb1v5: %d\n", milivolts ); - twl_vreg_get_voltage(isc->sc_vreg_dev, "vusb1v8", &milivolts); - device_printf( isc->sc_dev, "vusb1v8: %d\n", milivolts ); - twl_vreg_get_voltage(isc->sc_vreg_dev, "vusb3v1", &milivolts); - device_printf( isc->sc_dev, "vusb1v8: %d\n", milivolts ); -#endif - /* Enable Clocks for high speed USBHOST */ ti_prcm_clk_enable(USBHSHOST_CLK); @@ -411,28 +381,6 @@ /* Enable the USB TLL */ ti_prcm_clk_enable(USBTLL_CLK); - //check, if the ph is in suspend mode - device_printf( isc->sc_dev, "INSNREG05: 0x%08x\n", omap_ehci_read_4(isc, OMAP_USBHOST_INSNREG05_ULPI ) ); - - /* Set the timeout to 100ms*/ - timeout = (hz < 10) ? 1 : ((100 * hz) / 1000); - // perform a uhh reset - omap_uhh_write_4( isc, OMAP_USBHOST_UHH_SYSCONFIG, UHH_SYSCONFIG_SOFTRESET ); - - while( (omap_uhh_read_4( isc, OMAP_USBHOST_UHH_SYSSTATUS ) & 0x2) == 0 ) - { - /* Sleep for a tick */ - pause("USBRESET", 1); - - if (timeout-- == 0) { - device_printf(isc->sc_dev, "UHH reset operation timed out\n"); - ret = EINVAL; - goto err_sys_status; - } - } - device_printf(isc->sc_dev, "UHH RESET DONE\n"); - - /* Perform TLL soft reset, and wait until reset is complete */ omap_tll_write_4(isc, OMAP_USBTLL_SYSCONFIG, TLL_SYSCONFIG_SOFTRESET); @@ -466,13 +414,14 @@ TLL_SYSCONFIG_CACTIVITY); } else if (isc->ehci_rev == OMAP_EHCI_REV2) { -#if 0 + /* For OMAP44xx devices you have to enable the per-port clocks: * PHY_MODE - External ULPI clock * TTL_MODE - Internal UTMI clock * HSIC_MODE - Internal 480Mhz and 60Mhz clocks */ if (isc->ehci_rev == OMAP_EHCI_REV2) { +#if 0 if (isc->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) { ti_prcm_clk_set_source(USBP1_PHY_CLK, EXT_CLK); ti_prcm_clk_enable(USBP1_PHY_CLK); @@ -488,8 +437,8 @@ ti_prcm_clk_enable(USBP2_UTMI_CLK); else if (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_HSIC) ti_prcm_clk_enable(USBP2_HSIC_CLK); - } #endif + } } /* Put UHH in SmartIdle/SmartStandby mode */ @@ -569,10 +518,10 @@ * the root-hub is allowed to suspend. Writing 1 to this undocumented * register bit disables this feature and restores normal behavior." */ - +#if 0 omap_ehci_write_4(isc, OMAP_USBHOST_INSNREG04, OMAP_USBHOST_INSNREG04_DISABLE_UNSUSPEND); - +#endif /* If any of the ports are configured in TLL mode, enable them */ if ((isc->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) || @@ -842,7 +791,6 @@ /* save the device */ isc->sc_dev = dev; - isc->sc_vreg_dev = devclass_get_device(devclass_find("twl_vreg"), 0); /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev), @@ -1080,4 +1028,3 @@ static devclass_t ehci_devclass; DRIVER_MODULE(ehci, simplebus, ehci_driver, ehci_devclass, 0, 0); -MODULE_DEPEND(ehci, twl_vreg, 1, 1, 1); Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_usb.h ============================================================================== --- soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_usb.h Sat Aug 18 14:05:16 2012 (r240495) +++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_usb.h Sat Aug 18 16:50:12 2012 (r240496) @@ -132,6 +132,8 @@ + + /* TLL Register Set */ #define TLL_SYSCONFIG_CACTIVITY (1UL << 8) #define TLL_SYSCONFIG_SIDLE_SMART_IDLE (2UL << 3) @@ -197,7 +199,6 @@ #define UHH_HOSTCONFIG_P1_ULPI_BYPASS (1UL << 0) /* The following are on rev2 (OMAP44xx) of the EHCI only */ -#if 0 #define UHH_SYSCONFIG_IDLEMODE_MASK (3UL << 2) #define UHH_SYSCONFIG_IDLEMODE_NOIDLE (1UL << 2) #define UHH_SYSCONFIG_STANDBYMODE_MASK (3UL << 4) @@ -211,10 +212,8 @@ #define UHH_HOSTCONFIG_P2_MODE_ULPI_PHY (0UL << 18) #define UHH_HOSTCONFIG_P2_MODE_UTMI_PHY (1UL << 18) #define UHH_HOSTCONFIG_P2_MODE_HSIC (3UL << 18) -#endif #define ULPI_FUNC_CTRL_RESET (1 << 5) -#define ULPI_FUNC_CTRL_SUSPENDM (1 << 6) /*-------------------------------------------------------------------------*/ Modified: soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts ============================================================================== --- soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts Sat Aug 18 14:05:16 2012 (r240495) +++ soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts Sat Aug 18 16:50:12 2012 (r240496) @@ -184,12 +184,15 @@ compatible = "ti,twl4030"; reg = < 0x48 >; voltage-regulators = + "vusb1v5", "1500", + "vusb1v8", "1800", + "vusb3v1", "3100", "vusb1v5", "0", "vusb1v8", "0", - "vusb3v1", "0"; + "vusb3v1", "0", + "vaux2", "0"; }; }; - /* ehci@48064800 { compatible = "ti,ehci"; @@ -212,8 +215,7 @@ 0x48062000 0x1000 /* TLL * >; interrupts = < 77 >; interrupt-parent = <&AINTC>; - }; - */ + };*/ }; chosen {