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Date:      Mon, 16 May 2022 15:33:35 GMT
From:      Emmanuel Vadot <manu@FreeBSD.org>
To:        src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org
Subject:   git: cb5d34e59542 - stable/13 - arm64: rockchip: rk3328: Finish implementing clocks
Message-ID:  <202205161533.24GFXZGf020176@gitrepo.freebsd.org>

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The branch stable/13 has been updated by manu:

URL: https://cgit.FreeBSD.org/src/commit/?id=cb5d34e59542ac135d0c1c0992f388da68bbc6a6

commit cb5d34e59542ac135d0c1c0992f388da68bbc6a6
Author:     Emmanuel Vadot <manu@FreeBSD.org>
AuthorDate: 2021-09-15 16:33:38 +0000
Commit:     Emmanuel Vadot <manu@FreeBSD.org>
CommitDate: 2022-05-16 15:27:23 +0000

    arm64: rockchip: rk3328: Finish implementing clocks
    
    This finish (almost) the clocks implementations for the RK3328 SoC.
    The clocks are now correctly implemented respecting the clock hiearchy.
    The missing clocks are mostly the DDR clocks, implementing those is only
    useful for debugging as we will never set them in the kernel.
    The ARMCLK still needs to be rewritten so it looks closer to how the
    hardware is done.
    
    Tested-on: Rock64
    (cherry picked from commit cc2f9bbbad3b9cd81b8e66d57f9d34d8a42048dd)
---
 sys/arm64/rockchip/clk/rk3328_cru.c | 2096 ++++++++++++-----------------------
 1 file changed, 712 insertions(+), 1384 deletions(-)

diff --git a/sys/arm64/rockchip/clk/rk3328_cru.c b/sys/arm64/rockchip/clk/rk3328_cru.c
index 95a87cfd0e00..344bf3bcd7aa 100644
--- a/sys/arm64/rockchip/clk/rk3328_cru.c
+++ b/sys/arm64/rockchip/clk/rk3328_cru.c
@@ -1,7 +1,7 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
  *
- * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
+ * Copyright (c) 2018-2021 Emmanuel Vadot <manu@freebsd.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -49,18 +49,76 @@ __FBSDID("$FreeBSD$");
 
 #include <arm64/rockchip/clk/rk_cru.h>
 
+#define	CRU_CLKSEL_CON(x)	(0x100 + (x) * 0x4)
+
 /* Registers */
 #define	RK3328_GRF_SOC_CON4	0x410
 #define	RK3328_GRF_MAC_CON1	0x904
 #define	RK3328_GRF_MAC_CON2	0x908
 
-/* GATES */
-
+/* Exported clocks */
+
+#define	PLL_APLL		1
+#define	PLL_DPLL		2
+#define	PLL_CPLL		3
+#define	PLL_GPLL		4
+#define	PLL_NPLL		5
+#define	ARMCLK			6
+
+/* SCLK */
+#define	SCLK_RTC32K		30
+#define	SCLK_SDMMC_EXT		31
+#define	SCLK_SPI		32
+#define	SCLK_SDMMC		33
+#define	SCLK_SDIO		34
+#define	SCLK_EMMC		35
+#define	SCLK_TSADC		36
+#define	SCLK_SARADC		37
+#define	SCLK_UART0		38
+#define	SCLK_UART1		39
+#define	SCLK_UART2		40
 #define	SCLK_I2S0		41
 #define	SCLK_I2S1		42
 #define	SCLK_I2S2		43
 #define	SCLK_I2S1_OUT		44
 #define	SCLK_I2S2_OUT		45
+#define	SCLK_SPDIF		46
+#define	SCLK_TIMER0		47
+#define	SCLK_TIMER1		48
+#define	SCLK_TIMER2		49
+#define	SCLK_TIMER3		50
+#define	SCLK_TIMER4		51
+#define	SCLK_TIMER5		52
+#define	SCLK_WIFI		53
+#define	SCLK_CIF_OUT		54
+#define	SCLK_I2C0		55
+#define	SCLK_I2C1		56
+#define	SCLK_I2C2		57
+#define	SCLK_I2C3		58
+#define	SCLK_CRYPTO		59
+#define	SCLK_PWM		60
+#define	SCLK_PDM		61
+#define	SCLK_EFUSE		62
+#define	SCLK_OTP		63
+#define	SCLK_DDRCLK		64
+#define	SCLK_VDEC_CABAC		65
+#define	SCLK_VDEC_CORE		66
+#define	SCLK_VENC_DSP		67
+#define	SCLK_VENC_CORE		68
+#define	SCLK_RGA		69
+#define	SCLK_HDMI_SFC		70
+#define	SCLK_HDMI_CEC		71	/* Unused ? */
+#define	SCLK_USB3_REF		72
+#define	SCLK_USB3_SUSPEND	73
+#define	SCLK_SDMMC_DRV		74
+#define	SCLK_SDIO_DRV		75
+#define	SCLK_EMMC_DRV		76
+#define	SCLK_SDMMC_EXT_DRV	77
+#define	SCLK_SDMMC_SAMPLE	78
+#define	SCLK_SDIO_SAMPLE	79
+#define	SCLK_EMMC_SAMPLE	80
+#define	SCLK_SDMMC_EXT_SAMPLE	81
+#define	SCLK_VOP		82
 #define	SCLK_MAC2PHY_RXTX	83
 #define	SCLK_MAC2PHY_SRC	84
 #define	SCLK_MAC2PHY_REF	85
@@ -70,528 +128,553 @@ __FBSDID("$FreeBSD$");
 #define	SCLK_MAC2IO_REFOUT	89
 #define	SCLK_MAC2IO_REF		90
 #define	SCLK_MAC2IO_OUT		91
+#define	SCLK_TSP		92
+#define	SCLK_HSADC_TSP		93
+#define	SCLK_USB3PHY_REF	94
+#define	SCLK_REF_USB3OTG	95
 #define	SCLK_USB3OTG_REF	96
+#define	SCLK_USB3OTG_SUSPEND	97
+#define	SCLK_REF_USB3OTG_SRC	98
 #define	SCLK_MAC2IO_SRC		99
 #define	SCLK_MAC2IO		100
 #define	SCLK_MAC2PHY		101
 #define	SCLK_MAC2IO_EXT		102
+
+/* DCLK */
+#define	DCLK_LCDC		120
+#define	DCLK_HDMIPHY		121
+#define	HDMIPHY			122
+#define	USB480M			123
+#define	DCLK_LCDC_SRC		124
+
+/* ACLK */
+#define	ACLK_AXISRAM		130	/* Unused */
+#define	ACLK_VOP_PRE		131
 #define	ACLK_USB3OTG		132
-#define ACLK_GMAC		146
-#define ACLK_MAC2PHY		149
-#define ACLK_MAC2IO		150
+#define	ACLK_RGA_PRE		133
+#define	ACLK_DMAC		134	/* Unused */
+#define	ACLK_GPU		135
+#define	ACLK_BUS_PRE		136
+#define	ACLK_PERI_PRE		137
+#define	ACLK_RKVDEC_PRE		138
+#define	ACLK_RKVDEC		139
+#define	ACLK_RKVENC		140
+#define	ACLK_VPU_PRE		141
+#define	ACLK_VIO_PRE		142
+#define	ACLK_VPU		143
+#define	ACLK_VIO		144
+#define	ACLK_VOP		145
+#define	ACLK_GMAC		146
+#define	ACLK_H265		147
+#define	ACLK_H264		148
+#define	ACLK_MAC2PHY		149
+#define	ACLK_MAC2IO		150
+#define	ACLK_DCF		151
+#define	ACLK_TSP		152
 #define	ACLK_PERI		153
+#define	ACLK_RGA		154
+#define	ACLK_IEP		155
+#define	ACLK_CIF		156
+#define	ACLK_HDCP		157
+
+/* PCLK */
 #define	PCLK_GPIO0		200
 #define	PCLK_GPIO1		201
 #define	PCLK_GPIO2		202
 #define	PCLK_GPIO3		203
+#define	PCLK_GRF		204
 #define	PCLK_I2C0		205
 #define	PCLK_I2C1		206
 #define	PCLK_I2C2		207
 #define	PCLK_I2C3		208
+#define	PCLK_SPI		209
+#define	PCLK_UART0		210
+#define	PCLK_UART1		211
+#define	PCLK_UART2		212
 #define	PCLK_TSADC		213
-#define PCLK_GMAC		220
-#define PCLK_MAC2PHY		222
-#define PCLK_MAC2IO		223
+#define	PCLK_PWM		214
+#define	PCLK_TIMER		215
+#define	PCLK_BUS_PRE		216
+#define	PCLK_PERI_PRE		217	/* Unused */
+#define	PCLK_HDMI_CTRL		218	/* Unused */
+#define	PCLK_HDMI_PHY		219	/* Unused */
+#define	PCLK_GMAC		220
+#define	PCLK_H265		221
+#define	PCLK_MAC2PHY		222
+#define	PCLK_MAC2IO		223
 #define	PCLK_USB3PHY_OTG	224
 #define	PCLK_USB3PHY_PIPE	225
 #define	PCLK_USB3_GRF		226
+#define	PCLK_USB2_GRF		227
+#define	PCLK_HDMIPHY		228
+#define	PCLK_DDR		229
+#define	PCLK_PERI		230
+#define	PCLK_HDMI		231
+#define	PCLK_HDCP		232
+#define	PCLK_DCF		233
+#define	PCLK_SARADC		234
 #define	PCLK_ACODECPHY		235
+#define	PCLK_WDT		236	/* Controlled from the secure GRF */
+
+/* HCLK */
+#define	HCLK_PERI		308
+#define	HCLK_TSP		309
+#define	HCLK_GMAC		310	/* Unused */
 #define	HCLK_I2S0_8CH		311
 #define	HCLK_I2S1_8CH		312
 #define	HCLK_I2S2_2CH		313
+#define	HCLK_SPDIF_8CH		314
+#define	HCLK_VOP		315
+#define	HCLK_NANDC		316	/* Unused */
 #define	HCLK_SDMMC		317
 #define	HCLK_SDIO		318
 #define	HCLK_EMMC		319
 #define	HCLK_SDMMC_EXT		320
+#define	HCLK_RKVDEC_PRE		321
+#define	HCLK_RKVDEC		322
+#define	HCLK_RKVENC		323
+#define	HCLK_VPU_PRE		324
+#define	HCLK_VIO_PRE		325
+#define	HCLK_VPU		326
+/* 327 doesn't exists */
+#define	HCLK_BUS_PRE		328
+#define	HCLK_PERI_PRE		329	/* Unused */
+#define	HCLK_H264		330
+#define	HCLK_CIF		331
+#define	HCLK_OTG_PMU		332
+#define	HCLK_OTG		333
+#define	HCLK_HOST0		334
+#define	HCLK_HOST0_ARB		335
+#define	HCLK_CRYPTO_MST		336
+#define	HCLK_CRYPTO_SLV		337
+#define	HCLK_PDM		338
+#define	HCLK_IEP		339
+#define	HCLK_RGA		340
+#define	HCLK_HDCP		341
 
 static struct rk_cru_gate rk3328_gates[] = {
 	/* CRU_CLKGATE_CON0 */
-	CRU_GATE(0, "apll_core", "apll", 0x200, 0)
-	CRU_GATE(0, "dpll_core", "dpll", 0x200, 1)
-	CRU_GATE(0, "gpll_core", "gpll", 0x200, 2)
-	CRU_GATE(0, "npll_core", "npll", 0x200, 12)
+	CRU_GATE(0, "core_apll_clk", "apll", 0x200, 0)
+	CRU_GATE(0, "core_dpll_clk", "dpll", 0x200, 1)
+	CRU_GATE(0, "core_gpll_clk", "gpll", 0x200, 2)
+	/* Bit 3 bus_src_clk_en */
+	/* Bit 4 clk_ddrphy_src_en */
+	/* Bit 5 clk_ddrpd_src_en */
+	/* Bit 6 clk_ddrmon_en */
+	/* Bit 7-8 unused */
+	/* Bit 9 testclk_en */
+	CRU_GATE(SCLK_WIFI, "sclk_wifi", "sclk_wifi_c", 0x200, 10)
+	CRU_GATE(SCLK_RTC32K, "clk_rtc32k", "clk_rtc32k_c", 0x200, 11)
+	CRU_GATE(0, "core_npll_clk", "npll", 0x200, 12)
+	/* Bit 13-15 unused */
 
 	/* CRU_CLKGATE_CON1 */
+	/* Bit 0 unused */
+	CRU_GATE(0, "clk_i2s0_div", "clk_i2s0_div_c", 0x204, 1)
+	CRU_GATE(0, "clk_i2s0_frac", "clk_i2s0_frac_f", 0x204, 2)
 	CRU_GATE(SCLK_I2S0, "clk_i2s0", "clk_i2s0_mux", 0x204, 3)
+	CRU_GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 0x204, 4)
+	CRU_GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_f", 0x204, 5)
 	CRU_GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", 0x204, 6)
+	CRU_GATE(0, "clk_i2s1_out", "clk_i2s1_mux", 0x204, 7)
+	CRU_GATE(0, "clk_i2s2_div", "clk_i2s2_div_c", 0x204, 8)
+	CRU_GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_f", 0x204, 9)
 	CRU_GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", 0x204, 10)
+	CRU_GATE(0, "clk_i2s2_out", "clk_i2s2_mux", 0x204, 11)
+	CRU_GATE(0, "clk_spdif_div", "clk_spdif_div_c", 0x204, 12)
+	CRU_GATE(0, "clk_spdif_frac", "clk_spdif_frac_f", 0x204, 13)
+	CRU_GATE(0, "clk_uart0_div", "clk_uart0_div_c", 0x204, 14)
+	CRU_GATE(0, "clk_uart0_frac", "clk_uart0_frac_f", 0x204, 15)
+
+	/* CRU_CLKGATE_CON2 */
+	CRU_GATE(0, "clk_uart1_div", "clk_uart1_div_c", 0x208, 0)
+	CRU_GATE(0, "clk_uart1_frac", "clk_uart1_frac_f", 0x208, 1)
+	CRU_GATE(0, "clk_uart2_div", "clk_uart2_div_c", 0x208, 2)
+	CRU_GATE(0, "clk_uart2_frac", "clk_uart2_frac_f", 0x208, 3)
+	CRU_GATE(SCLK_CRYPTO, "clk_crypto", "clk_crypto_c", 0x208, 4)
+	CRU_GATE(SCLK_TSP, "clk_tsp", "clk_tsp_c", 0x208, 5)
+	CRU_GATE(SCLK_TSADC, "clk_tsadc_src", "clk_tsadc_c", 0x208, 6)
+	CRU_GATE(SCLK_SPI, "clk_spi", "clk_spi_c", 0x208, 7)
+	CRU_GATE(SCLK_PWM, "clk_pwm", "clk_pwm_c", 0x208, 8)
+	CRU_GATE(SCLK_I2C0, "clk_i2c0_src", "clk_i2c0_c", 0x208, 9)
+	CRU_GATE(SCLK_I2C1, "clk_i2c1_src", "clk_i2c1_c", 0x208, 10)
+	CRU_GATE(SCLK_I2C2, "clk_i2c2_src", "clk_i2c2_c", 0x208, 11)
+	CRU_GATE(SCLK_I2C3, "clk_i2c3_src", "clk_i2c3_c", 0x208, 12)
+	CRU_GATE(SCLK_EFUSE, "clk_efuse", "clk_efuse_c", 0x208, 13)
+	CRU_GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c", 0x208, 14)
+	CRU_GATE(SCLK_PDM, "clk_pdm", "clk_pdm_c", 0x208, 15)
+
+	/* CRU_CLKGATE_CON3 */
+	CRU_GATE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", "clk_mac2phy_src_c", 0x20c, 0)
+	CRU_GATE(SCLK_MAC2IO_SRC, "clk_mac2io_src", "clk_mac2io_src_c", 0x20c, 1)
+	CRU_GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_c", 0x20c, 2)
+	/* Bit 3 gmac_gpll_src_en Unused ? */
+	/* Bit 4 gmac_vpll_src_en Unused ? */
+	CRU_GATE(SCLK_MAC2IO_OUT, "clk_mac2io_out", "clk_mac2io_out_c", 0x20c, 5)
+	/* Bit 6-7 unused */
+	CRU_GATE(SCLK_OTP, "clk_otp", "clk_otp_c", 0x20c, 8)
+	/* Bit 9-15 unused */
 
 	/* CRU_CLKGATE_CON4 */
-	CRU_GATE(0, "gpll_peri", "gpll", 0x210, 0)
-	CRU_GATE(0, "cpll_peri", "cpll", 0x210, 1)
-	CRU_GATE(SCLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0x210, 7)
+	CRU_GATE(0, "periph_gclk_src", "gpll", 0x210, 0)
+	CRU_GATE(0, "periph_cclk_src", "cpll", 0x210, 1)
+	CRU_GATE(0, "hdmiphy_peri", "hdmiphy", 0x210, 2)
+	CRU_GATE(SCLK_SDMMC, "clk_mmc0_src", "clk_sdmmc_c", 0x210, 3)
+	CRU_GATE(SCLK_SDIO, "clk_sdio_src", "clk_sdio_c", 0x210, 4)
+	CRU_GATE(SCLK_EMMC, "clk_emmc_src", "clk_emmc_c", 0x210, 5)
+	CRU_GATE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", "clk_ref_usb3otg_src_c", 0x210, 6)
+	CRU_GATE(SCLK_USB3OTG_REF, "clk_usb3_otg0_ref", "xin24m", 0x210, 7)
+	CRU_GATE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", "clk_usb3otg_suspend_c", 0x210, 8)
+	/* Bit 9 clk_usb3phy_ref_25m_en */
+	CRU_GATE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", "clk_sdmmc_ext_c", 0x210, 10)
+	/* Bit 11-15 unused */
+
+	/* CRU_CLKGATE_CON5 */
+	CRU_GATE(ACLK_RGA_PRE, "aclk_rga_pre", "aclk_rga_pre_c", 0x214, 0)
+	CRU_GATE(SCLK_RGA, "sclk_rga", "sclk_rga_c", 0x214, 0)
+	CRU_GATE(ACLK_VIO_PRE, "aclk_vio_pre", "aclk_vio_pre_c", 0x214, 2)
+	CRU_GATE(SCLK_CIF_OUT, "clk_cif_src", "clk_cif_src_c", 0x214, 3)
+	CRU_GATE(SCLK_HDMI_SFC, "clk_hdmi_sfc", "xin24m", 0x214, 4)
+	CRU_GATE(ACLK_VOP_PRE, "aclk_vop_pre", "aclk_vop_pre_c", 0x214, 5)
+	CRU_GATE(DCLK_LCDC_SRC, "vop_dclk_src", "vop_dclk_src_c", 0x214, 6)
+	/* Bit 7-15 unused */
+
+	/* CRU_CLKGATE_CON6 */
+	CRU_GATE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", "aclk_rkvdec_c", 0x218, 0)
+	CRU_GATE(SCLK_VDEC_CABAC, "sclk_cabac", "sclk_cabac_c", 0x218, 1)
+	CRU_GATE(SCLK_VDEC_CORE, "sclk_vdec_core", "sclk_vdec_core_c", 0x218, 2)
+	CRU_GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_c", 0x218, 3)
+	CRU_GATE(SCLK_VENC_CORE, "sclk_venc", "sclk_venc_c", 0x218, 4)
+	CRU_GATE(ACLK_VPU_PRE, "aclk_vpu_pre", "aclk_vpu_pre_c", 0x218, 5)
+	CRU_GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 0x218, 6)
+	CRU_GATE(SCLK_VENC_DSP, "sclk_venc_dsp", "sclk_venc_dsp_c", 0x218, 7)
+	/* Bit 8-15 unused */
+
+	/* CRU_CLKGATE_CON7 */
+	/* Bit 0 aclk_core_en */
+	/* Bit 1 clk_core_periph_en */
+	/* Bit 2 clk_jtag_en */
+	/* Bit 3 unused */
+	/* Bit 4 pclk_ddr_en */
+	/* Bit 5-15 unused */
 
 	/* CRU_CLKGATE_CON8 */
+	CRU_GATE(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_pre_c", 0x220, 0)
+	CRU_GATE(HCLK_BUS_PRE, "hclk_bus_pre", "hclk_bus_pre_c", 0x220, 1)
+	CRU_GATE(PCLK_BUS_PRE, "pclk_bus_pre", "pclk_bus_pre_c", 0x220, 2)
 	CRU_GATE(0, "pclk_bus", "pclk_bus_pre", 0x220, 3)
-	CRU_GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0x220, 4)
+	CRU_GATE(0, "pclk_phy", "pclk_bus_pre", 0x220, 4)
+	CRU_GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0x220, 5)
+	CRU_GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0x220, 6)
+	CRU_GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0x220, 7)
+	CRU_GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0x220, 8)
+	CRU_GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0x220, 9)
+	CRU_GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0x220, 10)
+	/* Bit 11-15 unused */
 
-	/* CRU_CLKGATE_CON8 */
-	CRU_GATE(SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0x224, 7)
-	CRU_GATE(SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0x224, 6)
-	CRU_GATE(SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0x224, 5)
-	CRU_GATE(SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0x224, 4)
-	CRU_GATE(SCLK_MAC2PHY_REF, "clk_mac2phy_ref", "clk_mac2phy", 0x224, 3)
-	CRU_GATE(SCLK_MAC2PHY_RXTX, "clk_mac2phy_rxtx", "clk_mac2phy", 0x224, 1)
+	/* CRU_CLKGATE_CON9 */
+	CRU_GATE(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0x224, 0)
+	CRU_GATE(SCLK_MAC2PHY_RXTX, "clk_gmac2phy_rx", "clk_mac2phy", 0x224, 1)
+	CRU_GATE(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy_out_c", 0x224, 2)
+	CRU_GATE(SCLK_MAC2PHY_REF, "clk_gmac2phy_ref", "clk_mac2phy", 0x224, 3)
+	CRU_GATE(SCLK_MAC2IO_RX, "clk_gmac2io_rx", "clk_mac2io", 0x224, 4)
+	CRU_GATE(SCLK_MAC2IO_TX, "clk_gmac2io_tx", "clk_mac2io", 0x224, 5)
+	CRU_GATE(SCLK_MAC2IO_REFOUT, "clk_gmac2io_refout", "clk_mac2io", 0x224, 6)
+	CRU_GATE(SCLK_MAC2IO_REF, "clk_gmac2io_ref", "clk_mac2io", 0x224, 7)
+	/* Bit 8-15 unused */
 
 	/* CRU_CLKGATE_CON10 */
 	CRU_GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0x228, 0)
+	CRU_GATE(HCLK_PERI, "hclk_peri", "hclk_peri_c", 0x228, 1)
+	CRU_GATE(PCLK_PERI, "pclk_peri", "pclk_peri_c", 0x228, 2)
+	/* Bit 3-15 unused */
+
+	/* CRU_CLKGATE_CON11 */
+	CRU_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0x22C, 0)
+	/* Bit 1-3 unused */
+	CRU_GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 0x22C, 4)
+	/* Bit 5-7 unused */
+	CRU_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0x22C, 8)
+	/* Bit 9-15 unused */
+
+	/* CRU_CLKGATE_CON12 */
+	/* unused */
+
+	/* CRU_CLKGATE_CON13 */
+	/* Bit 0 aclk_core_niu_en */
+	/* Bit 1 aclk_gic400_en */
+	/* Bit 2-15 unused */
+
+	/* CRU_CLKGATE_CON14 */
+	CRU_GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0x238, 0)
+	CRU_GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0x238, 1)
+	/* Bit 2-15 unused */
 
 	/* CRU_CLKGATE_CON15*/
+	/* Bit 0 aclk_intmem_en Unused */
+	/* Bit 1 aclk_dmac_bus_en Unused */
+	/* Bit 2 hclk_rom_en Unused */
 	CRU_GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0x23C, 3)
 	CRU_GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0x23C, 4)
 	CRU_GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0x23C, 5)
+	CRU_GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 0x23C, 6)
+	CRU_GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0x23C, 7)
+	CRU_GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0x23C, 8)
+	CRU_GATE(0, "pclk_efuse", "pclk_bus", 0x23C, 9)
 	CRU_GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0x23C, 10)
+	CRU_GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0x23C, 11)
+	CRU_GATE(0, "aclk_bus_niu", "aclk_bus_pre", 0x23C, 12)
+	CRU_GATE(0, "hclk_bus_niu", "hclk_bus_pre", 0x23C, 13)
+	CRU_GATE(0, "pclk_bus_niu", "pclk_bus_pre", 0x23C, 14)
+	CRU_GATE(0, "pclk_phy_niu", "pclk_phy", 0x23C, 14)
+	/* Bit 15 pclk_phy_niu_en */
 
 	/* CRU_CLKGATE_CON16 */
-	CRU_GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0x23C, 0)
-	CRU_GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0x23C, 1)
-	CRU_GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0x23C, 2)
-	CRU_GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0x23C, 14)
-
+	CRU_GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0x240, 0)
+	CRU_GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0x240, 1)
+	CRU_GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0x240, 2)
+	CRU_GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 0x240, 3)
+	CRU_GATE(0, "pclk_stimer", "pclk_bus", 0x240, 4)
+	CRU_GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 0x240, 5)
+	CRU_GATE(PCLK_PWM, "pclk_pwm", "pclk_bus", 0x240, 6)
 	CRU_GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0x240, 7)
 	CRU_GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0x240, 8)
 	CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0x240, 9)
 	CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0x240, 10)
+	CRU_GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0x240, 11)
+	CRU_GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0x240, 12)
+	CRU_GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0x240, 13)
+	CRU_GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0x240, 14)
+	CRU_GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0x240, 15)
 
 	/* CRU_CLKGATE_CON17 */
-	CRU_GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", 0x244, 2)
-	CRU_GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0x244, 5)
+	CRU_GATE(PCLK_GRF, "pclk_grf", "pclk_bus", 0x244, 0)
+	/* Bit 1 unused */
+	CRU_GATE(PCLK_USB3_GRF, "pclk_usb3grf", "pclk_phy", 0x244, 2)
+	CRU_GATE(0, "pclk_ddrphy", "pclk_phy", 0x244, 3)
+	CRU_GATE(0, "pclk_cru", "pclk_bus", 0x244, 4)
+	CRU_GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy", 0x244, 5)
+	CRU_GATE(0, "pclk_sgrf", "pclk_bus", 0x244, 6)
+	CRU_GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy", 0x244, 7)
+	CRU_GATE(0, "pclk_vdacphy", "pclk_bus", 0x244, 8)
+	/* Bit 9 unused */
+	CRU_GATE(0, "pclk_sim", "pclk_bus", 0x244, 10)
+	CRU_GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0x244, 11)
+	CRU_GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0x244, 12)
+	/* Bit 13 clk_hsadc_0_tsp_en Depend on a gpio clock ? */
+	CRU_GATE(PCLK_USB2_GRF, "pclk_usb2grf", "pclk_phy", 0x244, 14)
+	CRU_GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0x244, 15)
+
+	/* CRU_CLKGATE_CON18 */
+	/* Bit 0 unused */
+	/* Bit 1 pclk_ddr_upctl_en */
+	/* Bit 2 pclk_ddr_msch_en */
+	/* Bit 3 pclk_ddr_mon_en */
+	/* Bit 4 aclk_ddr_upctl_en */
+	/* Bit 5 clk_ddr_upctl_en */
+	/* Bit 6 clk_ddr_msch_en */
+	/* Bit 7 pclk_ddrstdby_en */
+	/* Bit 8-15 unused */
 
 	/* CRU_CLKGATE_CON19 */
 	CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0x24C, 0)
 	CRU_GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0x24C, 1)
 	CRU_GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0x24C, 2)
+	/* Bit 3-5 unused */
+	CRU_GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0x24C, 6)
+	CRU_GATE(HCLK_HOST0_ARB, "hclk_host0_arg", "hclk_peri", 0x24C, 7)
+	CRU_GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0x24C, 8)
+	CRU_GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0x24C, 9)
+	/* Bit 10 unused */
+	CRU_GATE(0, "aclk_peri_niu", "aclk_peri", 0x24C, 11)
 	CRU_GATE(0, "hclk_peri_niu", "hclk_peri", 0x24C, 12)
 	CRU_GATE(0, "pclk_peri_niu", "hclk_peri", 0x24C, 13)
 	CRU_GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0x24C, 14)
 	CRU_GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0x24C, 15)
 
+	/* CRU_CLKGATE_CON20 */
+	/* unused */
+
+	/* CRU_CLKGATE_CON21 */
+	/* Bit 0-1 unused */
+	CRU_GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0x254, 2)
+	CRU_GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0x254, 3)
+	CRU_GATE(0, "aclk_vop_niu", "aclk_vop_pre", 0x254, 4)
+	CRU_GATE(0, "hclk_vop_niu", "hclk_vio_pre", 0x254, 5)
+	CRU_GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0x254, 6)
+	CRU_GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0x254, 7)
+	CRU_GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0x254, 8)
+	CRU_GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0x254, 9)
+	CRU_GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0x254, 10)
+	CRU_GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0x254, 11)
+	CRU_GATE(0, "hclk_ahb1tom", "hclk_vio_pre", 0x254, 12)
+	CRU_GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0x254, 13)
+	CRU_GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0x254, 14)
+	CRU_GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0x254, 15)
+
+	/* CRU_CLKGATE_CON22 */
+	CRU_GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0x258, 0)
+	CRU_GATE(0, "hclk_vio_niu", "hclk_vio_pre", 0x258, 1)
+	CRU_GATE(0, "aclk_vio_niu", "aclk_vio_pre", 0x258, 2)
+	CRU_GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0x258, 3)
+	CRU_GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0x258, 4)
+	CRU_GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0x258, 5)
+	/* Bit 6-15 unused */
+
+	/* CRU_CLKGATE_CON23 */
+	CRU_GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0x25C, 0)
+	CRU_GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0x25C, 1)
+	CRU_GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0x25C, 2)
+	CRU_GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0x25C, 3)
+	/* Bit 4-15 unused */
+
+	/* CRU_CLKGATE_CON24 */
+	CRU_GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0x260, 0)
+	CRU_GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0x260, 1)
+	CRU_GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 0x260, 2)
+	CRU_GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 0x260, 3)
+	/* Bit 4-15 unused */
+
+	/* CRU_CLKGATE_CON25 */
+	CRU_GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0x264, 0)
+	CRU_GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0x264, 1)
+	CRU_GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0x264, 2)
+	CRU_GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0x264, 3)
+	CRU_GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0x264, 4)
+	CRU_GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0x264, 5)
+	CRU_GATE(0, "aclk_axisram", "hclk_rkvenc", 0x264, 6)
+	/* Bit 7-15 unused */
+
 	/* CRU_CLKGATE_CON26 */
-	CRU_GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0x268, 0)
-	CRU_GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0x268, 1)
-	CRU_GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0x268, 2)
-	CRU_GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0x268, 3)
+	CRU_GATE(ACLK_MAC2PHY, "aclk_gmac2phy", "aclk_gmac", 0x268, 0)
+	CRU_GATE(PCLK_MAC2PHY, "pclk_gmac2phy", "pclk_gmac", 0x268, 1)
+	CRU_GATE(ACLK_MAC2IO, "aclk_gmac2io", "aclk_gmac", 0x268, 2)
+	CRU_GATE(PCLK_MAC2IO, "pclk_gmac2io", "pclk_gmac", 0x268, 3)
+	CRU_GATE(0, "aclk_gmac_niu", "aclk_gmac", 0x268, 4)
+	CRU_GATE(0, "pclk_gmac_niu", "pclk_gmac", 0x268, 5)
+	/* Bit 6-15 unused */
+
+	/* CRU_CLKGATE_CON27 */
+	/* Bit 0 clk_ddrphy_en */
+	/* Bit 1 clk4x_ddrphy_en */
 
 	/* CRU_CLKGATE_CON28 */
-	CRU_GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0x270, 1)
-	CRU_GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0x270, 2)
+	CRU_GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0x270, 0)
+	CRU_GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy", 0x270, 1)
+	CRU_GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy", 0x270, 2)
+	CRU_GATE(0, "pclk_pmu", "pclk_bus", 0x270, 3)
+	CRU_GATE(0, "pclk_otp", "pclk_bus", 0x270, 4)
+	/* Bit 5-15 unused */
 };
 
 /*
  * PLLs
  */
 
-#define PLL_APLL		1
-#define PLL_DPLL		2
-#define PLL_CPLL		3
-#define PLL_GPLL		4
-#define PLL_NPLL		5
+#define PLL_RATE(_hz, _ref, _fb, _post1, _post2, _dspd, _frac)		\
+{									\
+	.freq = _hz,							\
+	.refdiv = _ref,							\
+	.fbdiv = _fb,							\
+	.postdiv1 = _post1,						\
+	.postdiv2 = _post2,						\
+	.dsmpd = _dspd,							\
+	.frac = _frac,							\
+}
 
 static struct rk_clk_pll_rate rk3328_pll_rates[] = {
-	{
-		.freq = 1608000000,
-		.refdiv = 1,
-		.fbdiv = 67,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1584000000,
-		.refdiv = 1,
-		.fbdiv = 66,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1560000000,
-		.refdiv = 1,
-		.fbdiv = 65,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1536000000,
-		.refdiv = 1,
-		.fbdiv = 64,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1512000000,
-		.refdiv = 1,
-		.fbdiv = 63,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1488000000,
-		.refdiv = 1,
-		.fbdiv = 62,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1464000000,
-		.refdiv = 1,
-		.fbdiv = 61,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1440000000,
-		.refdiv = 1,
-		.fbdiv = 60,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1416000000,
-		.refdiv = 1,
-		.fbdiv = 59,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1392000000,
-		.refdiv = 1,
-		.fbdiv = 58,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1368000000,
-		.refdiv = 1,
-		.fbdiv = 57,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1344000000,
-		.refdiv = 1,
-		.fbdiv = 56,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1320000000,
-		.refdiv = 1,
-		.fbdiv = 55,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1296000000,
-		.refdiv = 1,
-		.fbdiv = 54,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1272000000,
-		.refdiv = 1,
-		.fbdiv = 53,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1248000000,
-		.refdiv = 1,
-		.fbdiv = 52,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1200000000,
-		.refdiv = 1,
-		.fbdiv = 50,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1188000000,
-		.refdiv = 2,
-		.fbdiv = 99,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1104000000,
-		.refdiv = 1,
-		.fbdiv = 46,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1100000000,
-		.refdiv = 12,
-		.fbdiv = 550,
-		.postdiv1 = 1,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1008000000,
-		.refdiv = 1,
-		.fbdiv = 84,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 1000000000,
-		.refdiv = 6,
-		.fbdiv = 500,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 984000000,
-		.refdiv = 1,
-		.fbdiv = 82,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 960000000,
-		.refdiv = 1,
-		.fbdiv = 80,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 936000000,
-		.refdiv = 1,
-		.fbdiv = 78,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 912000000,
-		.refdiv = 1,
-		.fbdiv = 76,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 900000000,
-		.refdiv = 4,
-		.fbdiv = 300,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 888000000,
-		.refdiv = 1,
-		.fbdiv = 74,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 864000000,
-		.refdiv = 1,
-		.fbdiv = 72,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 840000000,
-		.refdiv = 1,
-		.fbdiv = 70,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 816000000,
-		.refdiv = 1,
-		.fbdiv = 68,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 800000000,
-		.refdiv = 6,
-		.fbdiv = 400,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 700000000,
-		.refdiv = 6,
-		.fbdiv = 350,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 696000000,
-		.refdiv = 1,
-		.fbdiv = 58,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 600000000,
-		.refdiv = 1,
-		.fbdiv = 75,
-		.postdiv1 = 3,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 594000000,
-		.refdiv = 2,
-		.fbdiv = 99,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 504000000,
-		.refdiv = 1,
-		.fbdiv = 63,
-		.postdiv1 = 3,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 500000000,
-		.refdiv = 6,
-		.fbdiv = 250,
-		.postdiv1 = 2,
-		.postdiv2 = 1,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 408000000,
-		.refdiv = 1,
-		.fbdiv = 68,
-		.postdiv1 = 2,
-		.postdiv2 = 2,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 312000000,
-		.refdiv = 1,
-		.fbdiv = 52,
-		.postdiv1 = 2,
-		.postdiv2 = 2,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 216000000,
-		.refdiv = 1,
-		.fbdiv = 72,
-		.postdiv1 = 4,
-		.postdiv2 = 2,
-		.dsmpd = 1,
-	},
-	{
-		.freq = 96000000,
-		.refdiv = 1,
-		.fbdiv = 64,
-		.postdiv1 = 4,
-		.postdiv2 = 4,
-		.dsmpd = 1,
-	},
+	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+	PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+	PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
+	PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
+	PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
+	PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
+	PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
+	PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
+	PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
+	PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
+	PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
+	PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
+	PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
+	PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
+	PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
+	PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
+	PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
+	PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
+	PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
+	PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
+	PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
+	PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
+	PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
+	PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
+	PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
+	PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
+	PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+	PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
+	PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
+	PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
+	PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
+	PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+	PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
+	PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
+	PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
+	PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
*** 1374 LINES SKIPPED ***



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