From owner-svn-src-stable-10@FreeBSD.ORG Fri May 16 02:21:56 2014 Return-Path: Delivered-To: svn-src-stable-10@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 503F71A0; Fri, 16 May 2014 02:21:56 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 399AE2B0A; Fri, 16 May 2014 02:21:56 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s4G2Lu4E048344; Fri, 16 May 2014 02:21:56 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s4G2Lpqk048314; Fri, 16 May 2014 02:21:51 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201405160221.s4G2Lpqk048314@svn.freebsd.org> From: Ian Lepore Date: Fri, 16 May 2014 02:21:51 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r266207 - in stable/10/sys: arm/allwinner arm/arm arm/at91 arm/broadcom/bcm2835 arm/conf arm/freescale/imx arm/freescale/vybrid arm/include arm/lpc arm/mv arm/ti/am335x dev/aic7xxx/aicasm X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable-10@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: SVN commit messages for only the 10-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 May 2014 02:21:56 -0000 Author: ian Date: Fri May 16 02:21:51 2014 New Revision: 266207 URL: http://svnweb.freebsd.org/changeset/base/266207 Log: MFC r262534, r262548, r262549, r262552, r262568, r262581, r262583, r262584, r262585, r262587, r262696, r262712 Replace many pasted identical definitions of cpu_initclocks() with a common implementation in arm/machdep.c. aicasm: Don't complain about missing prototypes to ease bootstrap issues. Vybrid: Add driver for Inter-Integrated Circuit (I2C). imx6: Initialize the Low Power Mode bits to keep the ARM cores running during WFI. All our current ARM multi-core systems have all cores in one package with a shared L2 cache, reflect that in the common cpu_topo() routine. mpcore timer: Supply a DELAY() implementation via weak linkage, so that SoC-specific code can supply a better implementation. imx6: Add some rudimentary voltage control. Add an armv7 implementation of cpu_sleep(). Add __used attribute so that the DELAY implementation doesn't get optimized away as unreferenced, causing linker errors when trying to resolve the weak reference to the missing function. Added: stable/10/sys/arm/freescale/vybrid/vf_i2c.c - copied, changed from r262552, head/sys/arm/freescale/vybrid/vf_i2c.c Modified: stable/10/sys/arm/allwinner/timer.c stable/10/sys/arm/arm/cpufunc.c stable/10/sys/arm/arm/cpufunc_asm_armv7.S stable/10/sys/arm/arm/generic_timer.c stable/10/sys/arm/arm/machdep.c stable/10/sys/arm/arm/mp_machdep.c stable/10/sys/arm/arm/mpcore_timer.c stable/10/sys/arm/at91/uart_dev_at91usart.c stable/10/sys/arm/broadcom/bcm2835/bcm2835_systimer.c stable/10/sys/arm/conf/VYBRID.common stable/10/sys/arm/freescale/imx/imx6_anatop.c stable/10/sys/arm/freescale/imx/imx6_ccm.c stable/10/sys/arm/freescale/imx/imx6_ccmreg.h stable/10/sys/arm/freescale/imx/imx_gpt.c stable/10/sys/arm/freescale/vybrid/files.vybrid stable/10/sys/arm/include/cpufunc.h stable/10/sys/arm/include/machdep.h stable/10/sys/arm/lpc/lpc_timer.c stable/10/sys/arm/mv/timer.c stable/10/sys/arm/ti/am335x/am335x_dmtimer.c stable/10/sys/dev/aic7xxx/aicasm/Makefile Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/arm/allwinner/timer.c ============================================================================== --- stable/10/sys/arm/allwinner/timer.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/allwinner/timer.c Fri May 16 02:21:51 2014 (r266207) @@ -295,12 +295,6 @@ a10_timer_get_timerfreq(struct a10_timer return (sc->timer0_freq); } -void -cpu_initclocks(void) -{ - cpu_initclocks_bsp(); -} - static int a10_timer_hardclock(void *arg) { Modified: stable/10/sys/arm/arm/cpufunc.c ============================================================================== --- stable/10/sys/arm/arm/cpufunc.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/arm/cpufunc.c Fri May 16 02:21:51 2014 (r266207) @@ -1107,7 +1107,7 @@ struct cpu_functions cortexa_cpufuncs = cpufunc_nullop, /* flush_brnchtgt_C */ (void *)cpufunc_nullop, /* flush_brnchtgt_E */ - arm11_sleep, /* sleep */ + armv7_sleep, /* sleep */ /* Soft functions */ Modified: stable/10/sys/arm/arm/cpufunc_asm_armv7.S ============================================================================== --- stable/10/sys/arm/arm/cpufunc_asm_armv7.S Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/arm/cpufunc_asm_armv7.S Fri May 16 02:21:51 2014 (r266207) @@ -343,3 +343,9 @@ ENTRY(armv7_idcache_inv_all) bx lr @ return END(armv7_l1cache_inv_all) +ENTRY_NP(armv7_sleep) + dsb + wfi + bx lr +END(armv7_sleep) + Modified: stable/10/sys/arm/arm/generic_timer.c ============================================================================== --- stable/10/sys/arm/arm/generic_timer.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/arm/generic_timer.c Fri May 16 02:21:51 2014 (r266207) @@ -332,16 +332,6 @@ static devclass_t arm_tmr_devclass; DRIVER_MODULE(timer, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0); void -cpu_initclocks(void) -{ - - if (PCPU_GET(cpuid) == 0) - cpu_initclocks_bsp(); - else - cpu_initclocks_ap(); -} - -void DELAY(int usec) { int32_t counts, counts_per_usec; Modified: stable/10/sys/arm/arm/machdep.c ============================================================================== --- stable/10/sys/arm/arm/machdep.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/arm/machdep.c Fri May 16 02:21:51 2014 (r266207) @@ -456,6 +456,30 @@ cpu_idle_wakeup(int cpu) return (0); } +/* + * Most ARM platforms don't need to do anything special to init their clocks + * (they get intialized during normal device attachment), and by not defining a + * cpu_initclocks() function they get this generic one. Any platform that needs + * to do something special can just provide their own implementation, which will + * override this one due to the weak linkage. + */ +void +arm_generic_initclocks(void) +{ + +#ifndef NO_EVENTTIMERS +#ifdef SMP + if (PCPU_GET(cpuid) == 0) + cpu_initclocks_bsp(); + else + cpu_initclocks_ap(); +#else + cpu_initclocks_bsp(); +#endif +#endif +} +__weak_reference(arm_generic_initclocks, cpu_initclocks); + int fill_regs(struct thread *td, struct reg *regs) { Modified: stable/10/sys/arm/arm/mp_machdep.c ============================================================================== --- stable/10/sys/arm/arm/mp_machdep.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/arm/mp_machdep.c Fri May 16 02:21:51 2014 (r266207) @@ -371,7 +371,7 @@ struct cpu_group * cpu_topo(void) { - return (smp_topo_1level(CG_SHARE_L2, 1, 0)); + return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0)); } void Modified: stable/10/sys/arm/arm/mpcore_timer.c ============================================================================== --- stable/10/sys/arm/arm/mpcore_timer.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/arm/mpcore_timer.c Fri May 16 02:21:51 2014 (r266207) @@ -129,12 +129,12 @@ uint32_t platform_arm_tmr_freq = 0; static timecounter_get_t arm_tmr_get_timecount; static struct timecounter arm_tmr_timecount = { - .tc_name = "ARM MPCore Timecounter", + .tc_name = "MPCore", .tc_get_timecount = arm_tmr_get_timecount, .tc_poll_pps = NULL, .tc_counter_mask = ~0u, .tc_frequency = 0, - .tc_quality = 1000, + .tc_quality = 800, }; /** @@ -254,7 +254,7 @@ arm_tmr_probe(device_t dev) if (!ofw_bus_is_compatible(dev, "arm,mpcore-timers")) return (ENXIO); - device_set_desc(dev, "ARM Generic MPCore Timers"); + device_set_desc(dev, "ARM MPCore Timers"); return (BUS_PROBE_DEFAULT); } @@ -327,7 +327,7 @@ arm_tmr_attach(device_t dev) return (ENXIO); } - sc->et.et_name = "ARM MPCore Eventtimer"; + sc->et.et_name = "MPCore"; sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; sc->et.et_quality = 1000; @@ -359,25 +359,6 @@ static devclass_t arm_tmr_devclass; DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0); /** - * cpu_initclocks - called by system to initialise the cpu clocks - * - * This is a boilerplat function, most of the setup has already been done - * when the driver was attached. Therefore this function must only be called - * after the driver is attached. - * - * RETURNS - * nothing - */ -void -cpu_initclocks(void) -{ - if (PCPU_GET(cpuid) == 0) - cpu_initclocks_bsp(); - else - cpu_initclocks_ap(); -} - -/** * DELAY - Delay for at least usec microseconds. * @usec: number of microseconds to delay by * @@ -388,8 +369,8 @@ cpu_initclocks(void) * RETURNS: * nothing */ -void -DELAY(int usec) +static void __used /* Must emit function code for the weak ref below. */ +arm_tmr_DELAY(int usec) { int32_t counts_per_usec; int32_t counts; @@ -427,3 +408,11 @@ DELAY(int usec) first = last; } } + +/* + * Supply a DELAY() implementation via weak linkage. A platform may want to use + * the mpcore per-cpu eventtimers but provide its own DELAY() routine, + * especially when the core frequency can change on the fly. + */ +__weak_reference(arm_tmr_DELAY, DELAY); + Modified: stable/10/sys/arm/at91/uart_dev_at91usart.c ============================================================================== --- stable/10/sys/arm/at91/uart_dev_at91usart.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/at91/uart_dev_at91usart.c Fri May 16 02:21:51 2014 (r266207) @@ -279,7 +279,7 @@ at91_usart_init(struct uart_bas *bas, in * we don't want to hang here forever if the hardware is in a bad state. */ if (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY)) - DELAY(1000); + DELAY(10000); at91_usart_param(bas, baudrate, databits, stopbits, parity); Modified: stable/10/sys/arm/broadcom/bcm2835/bcm2835_systimer.c ============================================================================== --- stable/10/sys/arm/broadcom/bcm2835/bcm2835_systimer.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/broadcom/bcm2835/bcm2835_systimer.c Fri May 16 02:21:51 2014 (r266207) @@ -278,12 +278,6 @@ static devclass_t bcm_systimer_devclass; DRIVER_MODULE(bcm_systimer, simplebus, bcm_systimer_driver, bcm_systimer_devclass, 0, 0); void -cpu_initclocks(void) -{ - cpu_initclocks_bsp(); -} - -void DELAY(int usec) { int32_t counts; Modified: stable/10/sys/arm/conf/VYBRID.common ============================================================================== --- stable/10/sys/arm/conf/VYBRID.common Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/conf/VYBRID.common Fri May 16 02:21:51 2014 (r266207) @@ -124,8 +124,8 @@ device nand device uart # I2C (TWSI) -#device iic -#device iicbus +device iic +device iicbus # Ethernet device ether Modified: stable/10/sys/arm/freescale/imx/imx6_anatop.c ============================================================================== --- stable/10/sys/arm/freescale/imx/imx6_anatop.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/freescale/imx/imx6_anatop.c Fri May 16 02:21:51 2014 (r266207) @@ -66,6 +66,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include @@ -85,8 +86,11 @@ struct imx6_anatop_softc { struct resource *res[2]; uint32_t cpu_curhz; uint32_t cpu_curmhz; + uint32_t cpu_curmv; uint32_t cpu_minhz; + uint32_t cpu_minmv; uint32_t cpu_maxhz; + uint32_t cpu_maxmv; uint32_t refosc_hz; void *temp_intrhand; uint32_t temp_high_val; @@ -103,12 +107,15 @@ struct imx6_anatop_softc { static struct imx6_anatop_softc *imx6_anatop_sc; /* - * Table of CPU max frequencies. This is indexed by the max frequency value - * (0-3) from the ocotp CFG3 register. + * Tables of CPU max frequencies and corresponding voltages. This is indexed by + * the max frequency value (0-3) from the ocotp CFG3 register. */ static uint32_t imx6_cpu_maxhz_tab[] = { 792000000, 852000000, 996000000, 1200000000 }; +static uint32_t imx6_cpu_millivolt_tab[] = { + 1150, 1225, 1225, 1275 +}; #define TZ_ZEROC 2732 /* deci-Kelvin <-> deci-Celcius offset. */ @@ -130,6 +137,64 @@ imx6_anatop_write_4(bus_size_t offset, u bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value); } +static void +vdd_set(struct imx6_anatop_softc *sc, int mv) +{ + int newtarg, oldtarg; + uint32_t delay, pmureg; + static boolean_t init_done = false; + + /* + * The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM + * can't be more than 50mV above or 200mV below them. For now to keep + * things simple we set all three to the same value. + */ + + pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE); + oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK; + + /* Convert mV to target value. Clamp target to valid range. */ + if (mv < 725) + newtarg = 0x00; + else if (mv > 1450) + newtarg = 0x1F; + else + newtarg = (mv - 700) / 25; + + /* + * The first time through the 3 voltages might not be equal so use a + * long conservative delay. After that we need to delay 3uS for every + * 25mV step upward. No need to delay at all when lowering. + */ + if (init_done) { + if (newtarg == oldtarg) + return; + else if (newtarg > oldtarg) + delay = (newtarg - oldtarg) * 3; + else + delay = 0; + } else { + delay = 700 / 25 * 3; + init_done = true; + } + + /* + * Make the change and wait for it to take effect. + */ + pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK | + IMX6_ANALOG_PMU_REG1_TARG_MASK | + IMX6_ANALOG_PMU_REG2_TARG_MASK); + + pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT; + pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT; + pmureg |= newtarg << IMX6_ANALOG_PMU_REG2_TARG_SHIFT; + + imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg); + DELAY(delay); + sc->cpu_curmv = newtarg * 25 + 700; + device_printf(sc->dev, "voltage set to %u\n", sc->cpu_curmv); +} + static inline uint32_t cpufreq_hz_from_div(struct imx6_anatop_softc *sc, uint32_t div) { @@ -231,7 +296,9 @@ cpufreq_initialize(struct imx6_anatop_so FSL_OCOTP_CFG3_SPEED_MASK) >> FSL_OCOTP_CFG3_SPEED_SHIFT; sc->cpu_minhz = cpufreq_actual_hz(sc, imx6_cpu_maxhz_tab[0]); + sc->cpu_minmv = imx6_cpu_millivolt_tab[0]; sc->cpu_maxhz = cpufreq_actual_hz(sc, imx6_cpu_maxhz_tab[cfg3speed]); + sc->cpu_maxmv = imx6_cpu_millivolt_tab[cfg3speed]; /* * Set the CPU to maximum speed. @@ -241,6 +308,7 @@ cpufreq_initialize(struct imx6_anatop_so * basically assumes that a single core can't overheat before interrupts * are enabled; empirical testing shows that to be a safe assumption. */ + vdd_set(sc, sc->cpu_maxmv); cpufreq_set_clock(sc, sc->cpu_maxhz); device_printf(sc->dev, "CPU frequency %uMHz\n", sc->cpu_curmhz); } @@ -321,6 +389,7 @@ tempmon_gofast(struct imx6_anatop_softc { if (sc->cpu_curhz < sc->cpu_maxhz) { + vdd_set(sc, sc->cpu_maxmv); cpufreq_set_clock(sc, sc->cpu_maxhz); } } @@ -331,6 +400,7 @@ tempmon_goslow(struct imx6_anatop_softc if (sc->cpu_curhz > sc->cpu_minhz) { cpufreq_set_clock(sc, sc->cpu_minhz); + vdd_set(sc, sc->cpu_minmv); } } @@ -451,6 +521,11 @@ imx6_anatop_attach(device_t dev) if (err != 0) goto out; + SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), + OID_AUTO, "cpu_voltage", CTLFLAG_RD, + &sc->cpu_curmv, 0, "Current CPU voltage in millivolts"); + imx6_anatop_sc = sc; /* Modified: stable/10/sys/arm/freescale/imx/imx6_ccm.c ============================================================================== --- stable/10/sys/arm/freescale/imx/imx6_ccm.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/freescale/imx/imx6_ccm.c Fri May 16 02:21:51 2014 (r266207) @@ -92,6 +92,7 @@ ccm_attach(device_t dev) { struct ccm_softc *sc; int err, rid; + uint32_t reg; sc = device_get_softc(dev); err = 0; @@ -107,6 +108,26 @@ ccm_attach(device_t dev) } ccm_sc = sc; + + /* + * Configure the Low Power Mode setting to leave the ARM core power on + * when a WFI instruction is executed. This lets the MPCore timers and + * GIC continue to run, which is helpful when the only thing that can + * wake you up is an MPCore Private Timer interrupt delivered via GIC. + * + * XXX Based on the docs, setting CCM_CGPR_INT_MEM_CLK_LPM shouldn't be + * required when the LPM bits are set to LPM_RUN. But experimentally + * I've experienced a fairly rare lockup when not setting it. I was + * unable to prove conclusively that the lockup was related to power + * management or that this definitively fixes it. Revisit this. + */ + reg = RD4(sc, CCM_CGPR); + reg |= CCM_CGPR_INT_MEM_CLK_LPM; + WR4(sc, CCM_CGPR, reg); + reg = RD4(sc, CCM_CLPCR); + reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN; + WR4(sc, CCM_CLPCR, reg); + err = 0; out: Modified: stable/10/sys/arm/freescale/imx/imx6_ccmreg.h ============================================================================== --- stable/10/sys/arm/freescale/imx/imx6_ccmreg.h Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/freescale/imx/imx6_ccmreg.h Fri May 16 02:21:51 2014 (r266207) @@ -29,13 +29,20 @@ #ifndef IMX6_CCMREG_H #define IMX6_CCMREG_H -#define CCM_CCGR1 0x06C -#define CCM_CCGR2 0x070 -#define CCM_CCGR3 0x074 -#define CCM_CCGR4 0x078 -#define CCM_CCGR5 0x07C -#define CCM_CCGR6 0x080 -#define CCM_CMEOR 0x088 +#define CCM_CLPCR 0x054 +#define CCM_CLPCR_LPM_MASK 0x03 +#define CCM_CLPCR_LPM_RUN 0x00 +#define CCM_CLPCR_LPM_WAIT 0x01 +#define CCM_CLPCR_LPM_STOP 0x02 +#define CCM_CGPR 0x064 +#define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17) +#define CCM_CCGR1 0x06C +#define CCM_CCGR2 0x070 +#define CCM_CCGR3 0x074 +#define CCM_CCGR4 0x078 +#define CCM_CCGR5 0x07C +#define CCM_CCGR6 0x080 +#define CCM_CMEOR 0x088 #endif Modified: stable/10/sys/arm/freescale/imx/imx_gpt.c ============================================================================== --- stable/10/sys/arm/freescale/imx/imx_gpt.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/freescale/imx/imx_gpt.c Fri May 16 02:21:51 2014 (r266207) @@ -319,17 +319,6 @@ imx_gpt_get_timerfreq(struct imx_gpt_sof return (sc->clkfreq); } -void -cpu_initclocks(void) -{ - - if (imx_gpt_sc == NULL) { - panic("%s: i.MX GPT driver has not been initialized!", __func__); - } - - cpu_initclocks_bsp(); -} - static int imx_gpt_intr(void *arg) { Modified: stable/10/sys/arm/freescale/vybrid/files.vybrid ============================================================================== --- stable/10/sys/arm/freescale/vybrid/files.vybrid Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/freescale/vybrid/files.vybrid Fri May 16 02:21:51 2014 (r266207) @@ -23,6 +23,7 @@ arm/freescale/vybrid/vf_mscm.c standar arm/freescale/vybrid/vf_src.c standard arm/freescale/vybrid/vf_edma.c standard arm/freescale/vybrid/vf_dmamux.c standard +arm/freescale/vybrid/vf_i2c.c optional iicbus arm/freescale/vybrid/vf_tcon.c optional vt arm/freescale/vybrid/vf_dcu4.c optional vt arm/freescale/vybrid/vf_nfc.c optional nand Copied and modified: stable/10/sys/arm/freescale/vybrid/vf_i2c.c (from r262552, head/sys/arm/freescale/vybrid/vf_i2c.c) ============================================================================== --- head/sys/arm/freescale/vybrid/vf_i2c.c Thu Feb 27 09:59:15 2014 (r262552, copy source) +++ stable/10/sys/arm/freescale/vybrid/vf_i2c.c Fri May 16 02:21:51 2014 (r266207) @@ -104,11 +104,9 @@ struct i2c_softc { struct resource *res[2]; bus_space_tag_t bst; bus_space_handle_t bsh; - void *ih; device_t dev; device_t iicbus; struct mtx mutex; - int ibif; }; static struct resource_spec i2c_spec[] = { @@ -117,19 +115,6 @@ static struct resource_spec i2c_spec[] = { -1, 0 } }; -static void -i2c_intr(void *arg) -{ - struct i2c_softc *sc; - - sc = arg; - - if (READ1(sc, I2C_IBSR) & IBSR_IBIF) { - WRITE1(sc, I2C_IBSR, IBSR_IBIF); - sc->ibif = 1; - } -} - static int i2c_probe(device_t dev) { @@ -148,7 +133,6 @@ static int i2c_attach(device_t dev) { struct i2c_softc *sc; - int err; sc = device_get_softc(dev); sc->dev = dev; @@ -164,14 +148,6 @@ i2c_attach(device_t dev) sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); - /* Setup interrupt handler */ - err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, - NULL, i2c_intr, sc, &sc->ih); - if (err) { - device_printf(dev, "Unable to alloc interrupt resource.\n"); - return (ENXIO); - } - WRITE1(sc, I2C_IBIC, IBIC_BIIE); sc->iicbus = device_add_child(dev, "iicbus", -1); @@ -194,8 +170,10 @@ wait_for_iif(struct i2c_softc *sc) retry = 1000; while (retry --) { - if (sc->ibif == 1) + if (READ1(sc, I2C_IBSR) & IBSR_IBIF) { + WRITE1(sc, I2C_IBSR, IBSR_IBIF); return (IIC_NOERR); + } DELAY(10); } @@ -227,8 +205,10 @@ wait_for_icf(struct i2c_softc *sc) retry = 1000; while (retry --) { if (READ1(sc, I2C_IBSR) & IBSR_TCF) { - if (sc->ibif == 1) + if (READ1(sc, I2C_IBSR) & IBSR_IBIF) { + WRITE1(sc, I2C_IBSR, IBSR_IBIF); return (IIC_NOERR); + } } DELAY(10); } @@ -265,8 +245,6 @@ i2c_repeated_start(device_t dev, u_char DELAY(10); - sc->ibif = 0; - /* Write target address - LSB is R/W bit */ WRITE1(sc, I2C_IBDR, slave); @@ -310,8 +288,6 @@ i2c_start(device_t dev, u_char slave, in reg |= (IBCR_TXRX); WRITE1(sc, I2C_IBCR, reg); - sc->ibif = 0; - /* Write target address - LSB is R/W bit */ WRITE1(sc, I2C_IBDR, slave); @@ -407,7 +383,6 @@ i2c_read(device_t dev, char *buf, int le WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL); /* dummy read */ - sc->ibif = 0; READ1(sc, I2C_IBDR); DELAY(1000); } @@ -430,7 +405,6 @@ i2c_read(device_t dev, char *buf, int le WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_NOACK); } - sc->ibif = 0; *buf++ = READ1(sc, I2C_IBDR); (*read)++; } @@ -453,7 +427,6 @@ i2c_write(device_t dev, const char *buf, mtx_lock(&sc->mutex); while (*sent < len) { - sc->ibif = 0; WRITE1(sc, I2C_IBDR, *buf++); Modified: stable/10/sys/arm/include/cpufunc.h ============================================================================== --- stable/10/sys/arm/include/cpufunc.h Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/include/cpufunc.h Fri May 16 02:21:51 2014 (r266207) @@ -523,6 +523,7 @@ void armv7_setup (char *string); void armv7_context_switch (void); void armv7_drain_writebuf (void); void armv7_sev (void); +void armv7_sleep (int unused); u_int armv7_auxctrl (u_int, u_int); void pj4bv7_setup (char *string); void pj4b_config (void); Modified: stable/10/sys/arm/include/machdep.h ============================================================================== --- stable/10/sys/arm/include/machdep.h Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/include/machdep.h Fri May 16 02:21:51 2014 (r266207) @@ -32,6 +32,7 @@ vm_offset_t freebsd_parse_boot_param(str vm_offset_t linux_parse_boot_param(struct arm_boot_params *abp); vm_offset_t fake_preload_metadata(struct arm_boot_params *abp); vm_offset_t parse_boot_param(struct arm_boot_params *abp); +void arm_generic_initclocks(void); /* * Initialization functions called by the common initarm() function in Modified: stable/10/sys/arm/lpc/lpc_timer.c ============================================================================== --- stable/10/sys/arm/lpc/lpc_timer.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/lpc/lpc_timer.c Fri May 16 02:21:51 2014 (r266207) @@ -280,12 +280,6 @@ lpc_get_timecount(struct timecounter *tc } void -cpu_initclocks(void) -{ - cpu_initclocks_bsp(); -} - -void DELAY(int usec) { uint32_t counter; Modified: stable/10/sys/arm/mv/timer.c ============================================================================== --- stable/10/sys/arm/mv/timer.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/mv/timer.c Fri May 16 02:21:51 2014 (r266207) @@ -224,13 +224,6 @@ mv_timer_get_timecount(struct timecounte } void -cpu_initclocks(void) -{ - - cpu_initclocks_bsp(); -} - -void DELAY(int usec) { uint32_t val, val_temp; Modified: stable/10/sys/arm/ti/am335x/am335x_dmtimer.c ============================================================================== --- stable/10/sys/arm/ti/am335x/am335x_dmtimer.c Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/arm/ti/am335x/am335x_dmtimer.c Fri May 16 02:21:51 2014 (r266207) @@ -662,12 +662,6 @@ DRIVER_MODULE(am335x_dmtimer, simplebus, MODULE_DEPEND(am335x_dmtimer, am335x_prcm, 1, 1, 1); void -cpu_initclocks(void) -{ - cpu_initclocks_bsp(); -} - -void DELAY(int usec) { struct am335x_dmtimer_softc *sc; Modified: stable/10/sys/dev/aic7xxx/aicasm/Makefile ============================================================================== --- stable/10/sys/dev/aic7xxx/aicasm/Makefile Fri May 16 01:50:04 2014 (r266206) +++ stable/10/sys/dev/aic7xxx/aicasm/Makefile Fri May 16 02:21:51 2014 (r266207) @@ -39,3 +39,4 @@ LFLAGS+= -d .endif .include +CFLAGS+= -Wno-missing-prototypes