From owner-freebsd-mips@FreeBSD.ORG Wed Jul 1 04:42:28 2009 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id BEB76106564A for ; Wed, 1 Jul 2009 04:42:28 +0000 (UTC) (envelope-from neelnatu@yahoo.com) Received: from web34403.mail.mud.yahoo.com (web34403.mail.mud.yahoo.com [66.163.178.152]) by mx1.freebsd.org (Postfix) with SMTP id 8BB058FC0C for ; Wed, 1 Jul 2009 04:42:28 +0000 (UTC) (envelope-from neelnatu@yahoo.com) Received: (qmail 72844 invoked by uid 60001); 1 Jul 2009 04:42:28 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yahoo.com; s=s1024; t=1246423348; bh=gy3WkrNxgodIJVmC7xfQYgoDbiaqcSlC+HY5DNxPVD8=; h=Message-ID:X-YMail-OSG:Received:X-Mailer:Date:From:Subject:To:MIME-Version:Content-Type; b=z+S4WaXbI/59BadH7pdoVChsmU5TriITWkeRIELv7wPG3UT6wTBUWda7XrQt13oEDmyKtqxyBaVbeAjyrwWG5+zfSiAdPZNxih8gF86Xg8YtlGZ4kHke4pd41blD8dpmdkhSujsmN2E11p80zDBB5Md76Q9E5Bf3WkKpojagsqI= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:X-YMail-OSG:Received:X-Mailer:Date:From:Subject:To:MIME-Version:Content-Type; b=AxWKWYD7/Z5U0u/eFGRMPN4gtFZug2CQ3SZ8/1Etgrd1nn3J9jSwp3x3KmoG30gkYCoRhvy8CJygBbJj1XJe6FuwMuEQ/tq7CHgrQmRDABJRrhvV5EmxgB+/cvO263eR5SBcV/dUd5A1sE8CX9C7Dh0i28neZTezCRS2Cx+km0s=; Message-ID: <14584.70267.qm@web34403.mail.mud.yahoo.com> X-YMail-OSG: hqIw1EUVM1nL7_JdkyUhG89SAdNGkZBt770dvWBs6jy5Th3Pky6EYhhBGTWjkYsFfkFD6OO6cQrHb2F7KCJgDmgvoSEwrmL91hTVKwff9l9HxwT0QWozO11lLDD6JsDTWZcrkqwrwuk6uKTkSLSdrFMVOAiIHnMYDvSZ4dNxsW3v2CBG0u.qmKgrRXlvsBthmR2mrcBiiijau2gluKWUUlWnmHWuE1KdXIIFAktrNsxHEPri.sgq0NnMlAu6JGohH8bHHJW8INyuoaeeZl4IXwyDznWwU5g.0_IyzqwqMRuKsOPRxvAJ3iEfRQ7G3IruTgW4zDcAFhB_Fm0DJcUS6zXZQlHKn12eFHaUkL0- Received: from [198.95.226.228] by web34403.mail.mud.yahoo.com via HTTP; Tue, 30 Jun 2009 21:42:27 PDT X-Mailer: YahooMailClassic/5.4.17 YahooMailWebService/0.7.289.15 Date: Tue, 30 Jun 2009 21:42:27 -0700 (PDT) From: Neelkanth Natu To: freebsd-mips@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Subject: Machine Check exception during bootup X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Jul 2009 04:42:29 -0000 Hi, I was seeing machine check exception with the 'TLB Shutdown' bit set in the Status register during bootup. This would happen about 30% of the time at exactly the same place in Mips_TLBUpdate(). I was able to track this down to a bug in Mips_TLBFlush() which was using whatever address happened to be in the EntryHi register to initialize the TLB. If this address happened to be one that the system would subsequently instantiate in the TLB we would hit a machine check exception in Mips_TLBUpdate(). At first glance it appears that the code in Mips_TLBUpdate() should deal with this since it does a TLB probe and if the probe is successful it will do a 'tlbwi' to avoid the machine check. But 'tlbp' can only look at the 'asid' and 'vpn2' fields to do its job - it does not know if you are planning to install a TLB entry with 'Global' scope. IMO this is why we trip up on a machine check exception at the 'tlbwr' instruction in Mips_TLBUpdate(). I am attaching the diff to tlb.S that fixes this problem. best Neel ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/tlb.S#1 - /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S ==== @@ -81,14 +81,14 @@ #define _MFC0 dmfc0 #define _MTC0 dmtc0 #define WIRED_SHIFT 34 -#define PAGE_SHIFT 34 +#define PAGE_SHIFT 12 #else #define _SLL sll #define _SRL srl #define _MFC0 mfc0 #define _MTC0 mtc0 #define WIRED_SHIFT 2 -#define PAGE_SHIFT 2 +#define PAGE_SHIFT 12 #endif .set noreorder # Noreorder is default style! #if defined(ISA_MIPS32) @@ -232,22 +232,30 @@ mtc0 zero, COP_0_STATUS_REG # Disable interrupts ITLBNOPFIX mfc0 t1, COP_0_TLB_WIRED - li v0, MIPS_KSEG3_START + 0x0fff0000 # invalid address _MFC0 t0, COP_0_TLB_HI # Save the PID - _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid _MTC0 zero, COP_0_TLB_LO0 # Zero out low entry0. _MTC0 zero, COP_0_TLB_LO1 # Zero out low entry1. mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry. + + # + # Load invalid entry, each TLB entry should have it's own bogus + # address calculated by following expression: + # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; + # One bogus value for every TLB entry might cause MCHECK exception + # + sll t3, t1, PAGE_SHIFT + 1 + li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address + addu v0, t3 /* * Align the starting value (t1) and the upper bound (a0). */ 1: mtc0 t1, COP_0_TLB_INDEX # Set the index register. ITLBNOPFIX - _MTC0 t0, COP_0_TLB_HI # Restore the PID + _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid addu t1, t1, 1 # Increment index. - addu t0, t0, 8 * 1024 + addu v0, v0, 8 * 1024 MIPS_CPU_NOP_DELAY tlbwi # Write the TLB entry. MIPS_CPU_NOP_DELAY @@ -473,7 +481,17 @@ _MFC0 t4, COP_0_TLB_HI # Get current PID move t2, a0 mfc0 t1, COP_0_TLB_WIRED + + # + # Load invalid entry, each TLB entry should have it's own bogus + # address calculated by following expression: + # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; + # One bogus value for every TLB entry might cause MCHECK exception + # + sll t3, t1, PAGE_SHIFT + 1 li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address + addu v0, t3 + mfc0 t3, COP_0_TLB_PG_MASK # save current pgMask # do {} while (t1 < t2)