From owner-freebsd-hackers Thu Dec 13 12:12:39 2001 Delivered-To: freebsd-hackers@freebsd.org Received: from aslan.scsiguy.com (aslan.scsiguy.com [63.229.232.106]) by hub.freebsd.org (Postfix) with ESMTP id D0CD837B41B for ; Thu, 13 Dec 2001 12:12:36 -0800 (PST) Received: from scsiguy.com (localhost [127.0.0.1]) by aslan.scsiguy.com (8.11.5/8.11.5) with ESMTP id fBDKCSg09049; Thu, 13 Dec 2001 13:12:28 -0700 (MST) (envelope-from gibbs@scsiguy.com) Message-Id: <200112132012.fBDKCSg09049@aslan.scsiguy.com> To: =?ISO-8859-1?Q?G=E9rard_Roudier?= Cc: Greg Johnson , freebsd-hackers@FreeBSD.ORG Subject: Re: Bus master DMA problems In-Reply-To: Your message of "Thu, 13 Dec 2001 18:09:54 +0100." <20011213175415.R1979-100000@gerard> Date: Thu, 13 Dec 2001 13:12:28 -0700 From: "Justin T. Gibbs" Sender: owner-freebsd-hackers@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG > >There are a couple of rules in PCI you must have in mind when >synchronization between PCI devices is needed. > >1) Interrupts are not synchronization events. They just send attention to > the device driver (acts as SIGIO, for example). Some bridge may flush > posted buffers on interrupt, but since interrupt can be shared, you > must not rely on such mechanism. The exception to this rule are Message Signaled Interrupts. The interrupt is asserted by DMAing a token into a mailbox in the chipset. Since posted writes must complete in order, this mechanism guarantees that the interrupt is only asserted once any previous writes have completed. MSI is part of the PCI 2.2 spec, but may only start to be supported in upcoming PCI-X chipsets. I don't know when FreeBSD will gain support for MSI. -- Justin To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message