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From: Adrian Chadd <adrian@FreeBSD.org>
Date: Fri, 14 Feb 2014 04:03:17 +0000 (UTC)
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Subject: svn commit: r261869 - head/sys/mips/conf
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Author: adrian
Date: Fri Feb 14 04:03:17 2014
New Revision: 261869
URL: http://svnweb.freebsd.org/changeset/base/261869

Log:
  Add the ath0 EEPROM hints required to detect the on-chip wifi.
  
  This allows the on-chip wifi to work; however it's not yet fully
  tested.
  
  ath0: Vendor=0x168c, Device=0x0031
  ath0: Vendor=0x168c, Device=0x0031
  ath0: <Atheros AR934x> at mem 0x18100000-0x1811ffff irq 0 on nexus0
  ...
  ath0: [HT] enabling HT modes
  ath0: [HT] enabling short-GI in 20MHz mode
  ath0: [HT] 1 stream STBC receive enabled
  ath0: [HT] 1 stream STBC transmit enabled
  ath0: [HT] 2 RX streams; 2 TX streams
  
  Tested:
  
  * DB120 development board

Modified:
  head/sys/mips/conf/DB120.hints

Modified: head/sys/mips/conf/DB120.hints
==============================================================================
--- head/sys/mips/conf/DB120.hints	Fri Feb 14 03:45:49 2014	(r261868)
+++ head/sys/mips/conf/DB120.hints	Fri Feb 14 04:03:17 2014	(r261869)
@@ -50,6 +50,16 @@ hint.arge.1.media=1000
 hint.arge.1.fduplex=1
 hint.arge.1.miimode=1		# GMII
 
+# ath0: Where the ART is - last 64k in the flash
+hint.ath.0.eepromaddr=0x1fff0000
+hint.ath.0.eepromsize=16384
+
+# ath1: it's different; it's a PCIe attached device, so
+# we instead need to teach the PCIe bridge code about it
+# (ie, the 'early pci fixup' stuff that programs the PCIe
+# host registers on the NIC) and then we teach ath where
+# to find it.
+
 # flash layout:
 #
 # bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)