From owner-freebsd-smp Tue Nov 19 21:27:16 1996 Return-Path: owner-smp Received: (from root@localhost) by freefall.freebsd.org (8.7.5/8.7.3) id VAA04831 for smp-outgoing; Tue, 19 Nov 1996 21:27:16 -0800 (PST) Received: from databus.databus.com (databus.databus.com [198.186.154.34]) by freefall.freebsd.org (8.7.5/8.7.3) with SMTP id VAA04818 for ; Tue, 19 Nov 1996 21:27:08 -0800 (PST) From: Barney Wolff To: freebsd-smp@freebsd.org Date: Wed, 20 Nov 1996 00:17 EST Subject: Re: 8259 vs APIC Content-Type: text/plain Message-ID: <329296a60.1bae@databus.databus.com> Sender: owner-smp@freebsd.org X-Loop: FreeBSD.org Precedence: bulk > From: Steve Passe > Date: Tue, 19 Nov 1996 21:59:04 -0700 > > The 8259 ICU latches an INT that occurs while that INT is masked. > The IO APIC looses any INT occuring while that INT is masked. > Intel calls this a "design consideration", I call it "brain damage". If you'll pardon the naive opinion, it sounds to me as tho the 8259 is expecting to handle edge-triggered interrupts (as we know to be true, right?) but the APIC is really expecting level-triggered ints, where the int will still be there when it's finally unmasked. If that's true, I would be looking at a solution that kept the edge- triggered ints on the 8259, as nothing will save you otherwise. So what if you cut the rate of lost ints to one a week - that's utterly unacceptable for a production machine. I seem to recall that the APIC can be set for either edge or level, or am I just fantasizing again? Anyway, thanks for helping me understand the project better! Barney Wolff