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Date:      Tue, 22 May 2012 10:59:26 +0000 (UTC)
From:      Konstantin Belousov <kib@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r235782 - in head/sys: dev/agp modules/agp sys
Message-ID:  <201205221059.q4MAxQRM099642@svn.freebsd.org>

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Author: kib
Date: Tue May 22 10:59:26 2012
New Revision: 235782
URL: http://svn.freebsd.org/changeset/base/235782

Log:
  A rewrite of the i810 bits of the agp(4) driver.  New driver supports
  operations required by GEMified i915.ko. It also attaches to SandyBridge
  and IvyBridge CPU northbridges now.
  
  Sponsored by:	The FreeBSD Foundation
  MFC after:	1 month

Added:
  head/sys/dev/agp/agp_i810.h   (contents, props changed)
Modified:
  head/sys/dev/agp/agp.c
  head/sys/dev/agp/agp_i810.c
  head/sys/dev/agp/agp_if.m
  head/sys/dev/agp/agppriv.h
  head/sys/dev/agp/agpreg.h
  head/sys/dev/agp/agpvar.h
  head/sys/modules/agp/Makefile
  head/sys/sys/agpio.h

Modified: head/sys/dev/agp/agp.c
==============================================================================
--- head/sys/dev/agp/agp.c	Tue May 22 10:54:42 2012	(r235781)
+++ head/sys/dev/agp/agp.c	Tue May 22 10:59:26 2012	(r235782)
@@ -239,7 +239,8 @@ agp_generic_attach(device_t dev)
 		if (memsize <= agp_max[i][0])
 			break;
 	}
-	if (i == agp_max_size) i = agp_max_size - 1;
+	if (i == agp_max_size)
+		i = agp_max_size - 1;
 	sc->as_maxmem = agp_max[i][1] << 20U;
 
 	/*
@@ -803,6 +804,13 @@ agp_unbind_user(device_t dev, agp_unbind
 }
 
 static int
+agp_chipset_flush(device_t dev)
+{
+
+	return (AGP_CHIPSET_FLUSH(dev));
+}
+
+static int
 agp_open(struct cdev *kdev, int oflags, int devtype, struct thread *td)
 {
 	device_t dev = kdev->si_drv1;
@@ -869,6 +877,8 @@ agp_ioctl(struct cdev *kdev, u_long cmd,
 	case AGPIOC_UNBIND:
 		return agp_unbind_user(dev, (agp_unbind *)data);
 
+	case AGPIOC_CHIPSET_FLUSH:
+		return agp_chipset_flush(dev);
 	}
 
 	return EINVAL;

Modified: head/sys/dev/agp/agp_i810.c
==============================================================================
--- head/sys/dev/agp/agp_i810.c	Tue May 22 10:54:42 2012	(r235781)
+++ head/sys/dev/agp/agp_i810.c	Tue May 22 10:59:26 2012	(r235782)
@@ -1,8 +1,12 @@
 /*-
  * Copyright (c) 2000 Doug Rabson
  * Copyright (c) 2000 Ruslan Ermilov
+ * Copyright (c) 2011 The FreeBSD Foundation
  * All rights reserved.
  *
+ * Portions of this software were developed by Konstantin Belousov
+ * under sponsorship from the FreeBSD Foundation.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -28,6 +32,9 @@
 /*
  * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
  * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
+ *
+ * This is generic Intel GTT handling code, morphed from the AGP
+ * bridge code.
  */
 
 #include <sys/cdefs.h>
@@ -35,10 +42,17 @@ __FBSDID("$FreeBSD$");
 
 #include "opt_bus.h"
 
+#if 0
+#define	KTR_AGP_I810	KTR_DEV
+#else
+#define	KTR_AGP_I810	0
+#endif
+
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
+#include <sys/ktr.h>
 #include <sys/module.h>
 #include <sys/bus.h>
 #include <sys/lock.h>
@@ -47,8 +61,10 @@ __FBSDID("$FreeBSD$");
 
 #include <dev/agp/agppriv.h>
 #include <dev/agp/agpreg.h>
+#include <dev/agp/agp_i810.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcireg.h>
+#include <dev/pci/pci_private.h>
 
 #include <vm/vm.h>
 #include <vm/vm_object.h>
@@ -63,6 +79,88 @@ __FBSDID("$FreeBSD$");
 
 MALLOC_DECLARE(M_AGP);
 
+struct agp_i810_match;
+
+static int agp_i810_check_active(device_t bridge_dev);
+static int agp_i830_check_active(device_t bridge_dev);
+static int agp_i915_check_active(device_t bridge_dev);
+static int agp_sb_check_active(device_t bridge_dev);
+
+static void agp_82852_set_desc(device_t dev,
+    const struct agp_i810_match *match);
+static void agp_i810_set_desc(device_t dev, const struct agp_i810_match *match);
+
+static void agp_i810_dump_regs(device_t dev);
+static void agp_i830_dump_regs(device_t dev);
+static void agp_i855_dump_regs(device_t dev);
+static void agp_i915_dump_regs(device_t dev);
+static void agp_i965_dump_regs(device_t dev);
+static void agp_sb_dump_regs(device_t dev);
+
+static int agp_i810_get_stolen_size(device_t dev);
+static int agp_i830_get_stolen_size(device_t dev);
+static int agp_i915_get_stolen_size(device_t dev);
+static int agp_sb_get_stolen_size(device_t dev);
+
+static int agp_i810_get_gtt_mappable_entries(device_t dev);
+static int agp_i830_get_gtt_mappable_entries(device_t dev);
+static int agp_i915_get_gtt_mappable_entries(device_t dev);
+
+static int agp_i810_get_gtt_total_entries(device_t dev);
+static int agp_i965_get_gtt_total_entries(device_t dev);
+static int agp_gen5_get_gtt_total_entries(device_t dev);
+static int agp_sb_get_gtt_total_entries(device_t dev);
+
+static int agp_i810_install_gatt(device_t dev);
+static int agp_i830_install_gatt(device_t dev);
+
+static void agp_i810_deinstall_gatt(device_t dev);
+static void agp_i830_deinstall_gatt(device_t dev);
+
+static void agp_i810_install_gtt_pte(device_t dev, u_int index,
+    vm_offset_t physical, int flags);
+static void agp_i830_install_gtt_pte(device_t dev, u_int index,
+    vm_offset_t physical, int flags);
+static void agp_i915_install_gtt_pte(device_t dev, u_int index,
+    vm_offset_t physical, int flags);
+static void agp_i965_install_gtt_pte(device_t dev, u_int index,
+    vm_offset_t physical, int flags);
+static void agp_g4x_install_gtt_pte(device_t dev, u_int index,
+    vm_offset_t physical, int flags);
+static void agp_sb_install_gtt_pte(device_t dev, u_int index,
+    vm_offset_t physical, int flags);
+
+static void agp_i810_write_gtt(device_t dev, u_int index, uint32_t pte);
+static void agp_i915_write_gtt(device_t dev, u_int index, uint32_t pte);
+static void agp_i965_write_gtt(device_t dev, u_int index, uint32_t pte);
+static void agp_g4x_write_gtt(device_t dev, u_int index, uint32_t pte);
+static void agp_sb_write_gtt(device_t dev, u_int index, uint32_t pte);
+
+static u_int32_t agp_i810_read_gtt_pte(device_t dev, u_int index);
+static u_int32_t agp_i915_read_gtt_pte(device_t dev, u_int index);
+static u_int32_t agp_i965_read_gtt_pte(device_t dev, u_int index);
+static u_int32_t agp_g4x_read_gtt_pte(device_t dev, u_int index);
+
+static vm_paddr_t agp_i810_read_gtt_pte_paddr(device_t dev, u_int index);
+static vm_paddr_t agp_i915_read_gtt_pte_paddr(device_t dev, u_int index);
+static vm_paddr_t agp_sb_read_gtt_pte_paddr(device_t dev, u_int index);
+
+static int agp_i810_set_aperture(device_t dev, u_int32_t aperture);
+static int agp_i830_set_aperture(device_t dev, u_int32_t aperture);
+static int agp_i915_set_aperture(device_t dev, u_int32_t aperture);
+
+static int agp_i810_chipset_flush_setup(device_t dev);
+static int agp_i915_chipset_flush_setup(device_t dev);
+static int agp_i965_chipset_flush_setup(device_t dev);
+
+static void agp_i810_chipset_flush_teardown(device_t dev);
+static void agp_i915_chipset_flush_teardown(device_t dev);
+static void agp_i965_chipset_flush_teardown(device_t dev);
+
+static void agp_i810_chipset_flush(device_t dev);
+static void agp_i830_chipset_flush(device_t dev);
+static void agp_i915_chipset_flush(device_t dev);
+
 enum {
 	CHIP_I810,	/* i810/i815 */
 	CHIP_I830,	/* 830M/845G */
@@ -72,6 +170,7 @@ enum {
 	CHIP_G33,	/* G33/Q33/Q35 */
 	CHIP_IGD,	/* Pineview */
 	CHIP_G4X,	/* G45/Q45 */
+	CHIP_SB,	/* SandyBridge */
 };
 
 /* The i810 through i855 have the registers at BAR 1, and the GATT gets
@@ -96,19 +195,308 @@ static struct resource_spec agp_i965_res
 	{ -1, 0 }
 };
 
+static struct resource_spec agp_g4x_res_spec[] = {
+	{ SYS_RES_MEMORY, AGP_G4X_MMADR, RF_ACTIVE | RF_SHAREABLE },
+	{ SYS_RES_MEMORY, AGP_G4X_GTTADR, RF_ACTIVE | RF_SHAREABLE },
+	{ -1, 0 }
+};
+
 struct agp_i810_softc {
 	struct agp_softc agp;
 	u_int32_t initial_aperture;	/* aperture size at startup */
 	struct agp_gatt *gatt;
-	int chiptype;			/* i810-like or i830 */
 	u_int32_t dcache_size;		/* i810 only */
-	u_int32_t stolen;		/* number of i830/845 gtt entries for stolen memory */
+	u_int32_t stolen;		/* number of i830/845 gtt
+					   entries for stolen memory */
+	u_int stolen_size;		/* BIOS-reserved graphics memory */
+	u_int gtt_total_entries;	/* Total number of gtt ptes */
+	u_int gtt_mappable_entries;	/* Number of gtt ptes mappable by CPU */
 	device_t bdev;			/* bridge device */
-
 	void *argb_cursor;		/* contigmalloc area for ARGB cursor */
-
-	struct resource_spec * sc_res_spec;
 	struct resource *sc_res[2];
+	const struct agp_i810_match *match;
+	int sc_flush_page_rid;
+	struct resource *sc_flush_page_res;
+	void *sc_flush_page_vaddr;
+	int sc_bios_allocated_flush_page;
+};
+
+static device_t intel_agp;
+
+struct agp_i810_driver {
+	int chiptype;
+	int gen;
+	int busdma_addr_mask_sz;
+	struct resource_spec *res_spec;
+	int (*check_active)(device_t);
+	void (*set_desc)(device_t, const struct agp_i810_match *);
+	void (*dump_regs)(device_t);
+	int (*get_stolen_size)(device_t);
+	int (*get_gtt_total_entries)(device_t);
+	int (*get_gtt_mappable_entries)(device_t);
+	int (*install_gatt)(device_t);
+	void (*deinstall_gatt)(device_t);
+	void (*write_gtt)(device_t, u_int, uint32_t);
+	void (*install_gtt_pte)(device_t, u_int, vm_offset_t, int);
+	u_int32_t (*read_gtt_pte)(device_t, u_int);
+	vm_paddr_t (*read_gtt_pte_paddr)(device_t , u_int);
+	int (*set_aperture)(device_t, u_int32_t);
+	int (*chipset_flush_setup)(device_t);
+	void (*chipset_flush_teardown)(device_t);
+	void (*chipset_flush)(device_t);
+};
+
+static const struct agp_i810_driver agp_i810_i810_driver = {
+	.chiptype = CHIP_I810,
+	.gen = 1,
+	.busdma_addr_mask_sz = 32,
+	.res_spec = agp_i810_res_spec,
+	.check_active = agp_i810_check_active,
+	.set_desc = agp_i810_set_desc,
+	.dump_regs = agp_i810_dump_regs,
+	.get_stolen_size = agp_i810_get_stolen_size,
+	.get_gtt_mappable_entries = agp_i810_get_gtt_mappable_entries,
+	.get_gtt_total_entries = agp_i810_get_gtt_total_entries,
+	.install_gatt = agp_i810_install_gatt,
+	.deinstall_gatt = agp_i810_deinstall_gatt,
+	.write_gtt = agp_i810_write_gtt,
+	.install_gtt_pte = agp_i810_install_gtt_pte,
+	.read_gtt_pte = agp_i810_read_gtt_pte,
+	.read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
+	.set_aperture = agp_i810_set_aperture,
+	.chipset_flush_setup = agp_i810_chipset_flush_setup,
+	.chipset_flush_teardown = agp_i810_chipset_flush_teardown,
+	.chipset_flush = agp_i810_chipset_flush,
+};
+
+static const struct agp_i810_driver agp_i810_i815_driver = {
+	.chiptype = CHIP_I810,
+	.gen = 2,
+	.busdma_addr_mask_sz = 32,
+	.res_spec = agp_i810_res_spec,
+	.check_active = agp_i810_check_active,
+	.set_desc = agp_i810_set_desc,
+	.dump_regs = agp_i810_dump_regs,
+	.get_stolen_size = agp_i810_get_stolen_size,
+	.get_gtt_mappable_entries = agp_i830_get_gtt_mappable_entries,
+	.get_gtt_total_entries = agp_i810_get_gtt_total_entries,
+	.install_gatt = agp_i810_install_gatt,
+	.deinstall_gatt = agp_i810_deinstall_gatt,
+	.write_gtt = agp_i810_write_gtt,
+	.install_gtt_pte = agp_i810_install_gtt_pte,
+	.read_gtt_pte = agp_i810_read_gtt_pte,
+	.read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
+	.set_aperture = agp_i810_set_aperture,
+	.chipset_flush_setup = agp_i810_chipset_flush_setup,
+	.chipset_flush_teardown = agp_i810_chipset_flush_teardown,
+	.chipset_flush = agp_i830_chipset_flush,
+};
+
+static const struct agp_i810_driver agp_i810_i830_driver = {
+	.chiptype = CHIP_I830,
+	.gen = 2,
+	.busdma_addr_mask_sz = 32,
+	.res_spec = agp_i810_res_spec,
+	.check_active = agp_i830_check_active,
+	.set_desc = agp_i810_set_desc,
+	.dump_regs = agp_i830_dump_regs,
+	.get_stolen_size = agp_i830_get_stolen_size,
+	.get_gtt_mappable_entries = agp_i830_get_gtt_mappable_entries,
+	.get_gtt_total_entries = agp_i810_get_gtt_total_entries,
+	.install_gatt = agp_i830_install_gatt,
+	.deinstall_gatt = agp_i830_deinstall_gatt,
+	.write_gtt = agp_i810_write_gtt,
+	.install_gtt_pte = agp_i830_install_gtt_pte,
+	.read_gtt_pte = agp_i810_read_gtt_pte,
+	.read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
+	.set_aperture = agp_i830_set_aperture,
+	.chipset_flush_setup = agp_i810_chipset_flush_setup,
+	.chipset_flush_teardown = agp_i810_chipset_flush_teardown,
+	.chipset_flush = agp_i830_chipset_flush,
+};
+
+static const struct agp_i810_driver agp_i810_i855_driver = {
+	.chiptype = CHIP_I855,
+	.gen = 2,
+	.busdma_addr_mask_sz = 32,
+	.res_spec = agp_i810_res_spec,
+	.check_active = agp_i830_check_active,
+	.set_desc = agp_82852_set_desc,
+	.dump_regs = agp_i855_dump_regs,
+	.get_stolen_size = agp_i915_get_stolen_size,
+	.get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
+	.get_gtt_total_entries = agp_i810_get_gtt_total_entries,
+	.install_gatt = agp_i830_install_gatt,
+	.deinstall_gatt = agp_i830_deinstall_gatt,
+	.write_gtt = agp_i810_write_gtt,
+	.install_gtt_pte = agp_i830_install_gtt_pte,
+	.read_gtt_pte = agp_i810_read_gtt_pte,
+	.read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
+	.set_aperture = agp_i830_set_aperture,
+	.chipset_flush_setup = agp_i810_chipset_flush_setup,
+	.chipset_flush_teardown = agp_i810_chipset_flush_teardown,
+	.chipset_flush = agp_i830_chipset_flush,
+};
+
+static const struct agp_i810_driver agp_i810_i865_driver = {
+	.chiptype = CHIP_I855,
+	.gen = 2,
+	.busdma_addr_mask_sz = 32,
+	.res_spec = agp_i810_res_spec,
+	.check_active = agp_i830_check_active,
+	.set_desc = agp_i810_set_desc,
+	.dump_regs = agp_i855_dump_regs,
+	.get_stolen_size = agp_i915_get_stolen_size,
+	.get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
+	.get_gtt_total_entries = agp_i810_get_gtt_total_entries,
+	.install_gatt = agp_i830_install_gatt,
+	.deinstall_gatt = agp_i830_deinstall_gatt,
+	.write_gtt = agp_i810_write_gtt,
+	.install_gtt_pte = agp_i830_install_gtt_pte,
+	.read_gtt_pte = agp_i810_read_gtt_pte,
+	.read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
+	.set_aperture = agp_i915_set_aperture,
+	.chipset_flush_setup = agp_i810_chipset_flush_setup,
+	.chipset_flush_teardown = agp_i810_chipset_flush_teardown,
+	.chipset_flush = agp_i830_chipset_flush,
+};
+
+static const struct agp_i810_driver agp_i810_i915_driver = {
+	.chiptype = CHIP_I915,
+	.gen = 3,
+	.busdma_addr_mask_sz = 32,
+	.res_spec = agp_i915_res_spec,
+	.check_active = agp_i915_check_active,
+	.set_desc = agp_i810_set_desc,
+	.dump_regs = agp_i915_dump_regs,
+	.get_stolen_size = agp_i915_get_stolen_size,
+	.get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
+	.get_gtt_total_entries = agp_i810_get_gtt_total_entries,
+	.install_gatt = agp_i830_install_gatt,
+	.deinstall_gatt = agp_i830_deinstall_gatt,
+	.write_gtt = agp_i915_write_gtt,
+	.install_gtt_pte = agp_i915_install_gtt_pte,
+	.read_gtt_pte = agp_i915_read_gtt_pte,
+	.read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
+	.set_aperture = agp_i915_set_aperture,
+	.chipset_flush_setup = agp_i915_chipset_flush_setup,
+	.chipset_flush_teardown = agp_i915_chipset_flush_teardown,
+	.chipset_flush = agp_i915_chipset_flush,
+};
+
+static const struct agp_i810_driver agp_i810_g965_driver = {
+	.chiptype = CHIP_I965,
+	.gen = 4,
+	.busdma_addr_mask_sz = 36,
+	.res_spec = agp_i965_res_spec,
+	.check_active = agp_i915_check_active,
+	.set_desc = agp_i810_set_desc,
+	.dump_regs = agp_i965_dump_regs,
+	.get_stolen_size = agp_i915_get_stolen_size,
+	.get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
+	.get_gtt_total_entries = agp_i965_get_gtt_total_entries,
+	.install_gatt = agp_i830_install_gatt,
+	.deinstall_gatt = agp_i830_deinstall_gatt,
+	.write_gtt = agp_i965_write_gtt,
+	.install_gtt_pte = agp_i965_install_gtt_pte,
+	.read_gtt_pte = agp_i965_read_gtt_pte,
+	.read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
+	.set_aperture = agp_i915_set_aperture,
+	.chipset_flush_setup = agp_i965_chipset_flush_setup,
+	.chipset_flush_teardown = agp_i965_chipset_flush_teardown,
+	.chipset_flush = agp_i915_chipset_flush,
+};
+
+static const struct agp_i810_driver agp_i810_g33_driver = {
+	.chiptype = CHIP_G33,
+	.gen = 3,
+	.busdma_addr_mask_sz = 36,
+	.res_spec = agp_i915_res_spec,
+	.check_active = agp_i915_check_active,
+	.set_desc = agp_i810_set_desc,
+	.dump_regs = agp_i965_dump_regs,
+	.get_stolen_size = agp_i915_get_stolen_size,
+	.get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
+	.get_gtt_total_entries = agp_i965_get_gtt_total_entries,
+	.install_gatt = agp_i830_install_gatt,
+	.deinstall_gatt = agp_i830_deinstall_gatt,
+	.write_gtt = agp_i915_write_gtt,
+	.install_gtt_pte = agp_i915_install_gtt_pte,
+	.read_gtt_pte = agp_i915_read_gtt_pte,
+	.read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
+	.set_aperture = agp_i915_set_aperture,
+	.chipset_flush_setup = agp_i965_chipset_flush_setup,
+	.chipset_flush_teardown = agp_i965_chipset_flush_teardown,
+	.chipset_flush = agp_i915_chipset_flush,
+};
+
+static const struct agp_i810_driver agp_i810_igd_driver = {
+	.chiptype = CHIP_IGD,
+	.gen = 3,
+	.busdma_addr_mask_sz = 36,
+	.res_spec = agp_i915_res_spec,
+	.check_active = agp_i915_check_active,
+	.set_desc = agp_i810_set_desc,
+	.dump_regs = agp_i915_dump_regs,
+	.get_stolen_size = agp_i915_get_stolen_size,
+	.get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
+	.get_gtt_total_entries = agp_i965_get_gtt_total_entries,
+	.install_gatt = agp_i830_install_gatt,
+	.deinstall_gatt = agp_i830_deinstall_gatt,
+	.write_gtt = agp_i915_write_gtt,
+	.install_gtt_pte = agp_i915_install_gtt_pte,
+	.read_gtt_pte = agp_i915_read_gtt_pte,
+	.read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
+	.set_aperture = agp_i915_set_aperture,
+	.chipset_flush_setup = agp_i965_chipset_flush_setup,
+	.chipset_flush_teardown = agp_i965_chipset_flush_teardown,
+	.chipset_flush = agp_i915_chipset_flush,
+};
+
+static const struct agp_i810_driver agp_i810_g4x_driver = {
+	.chiptype = CHIP_G4X,
+	.gen = 5,
+	.busdma_addr_mask_sz = 36,
+	.res_spec = agp_i965_res_spec,
+	.check_active = agp_i915_check_active,
+	.set_desc = agp_i810_set_desc,
+	.dump_regs = agp_i965_dump_regs,
+	.get_stolen_size = agp_i915_get_stolen_size,
+	.get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
+	.get_gtt_total_entries = agp_gen5_get_gtt_total_entries,
+	.install_gatt = agp_i830_install_gatt,
+	.deinstall_gatt = agp_i830_deinstall_gatt,
+	.write_gtt = agp_g4x_write_gtt,
+	.install_gtt_pte = agp_g4x_install_gtt_pte,
+	.read_gtt_pte = agp_g4x_read_gtt_pte,
+	.read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
+	.set_aperture = agp_i915_set_aperture,
+	.chipset_flush_setup = agp_i965_chipset_flush_setup,
+	.chipset_flush_teardown = agp_i965_chipset_flush_teardown,
+	.chipset_flush = agp_i915_chipset_flush,
+};
+
+static const struct agp_i810_driver agp_i810_sb_driver = {
+	.chiptype = CHIP_SB,
+	.gen = 6,
+	.busdma_addr_mask_sz = 40,
+	.res_spec = agp_g4x_res_spec,
+	.check_active = agp_sb_check_active,
+	.set_desc = agp_i810_set_desc,
+	.dump_regs = agp_sb_dump_regs,
+	.get_stolen_size = agp_sb_get_stolen_size,
+	.get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
+	.get_gtt_total_entries = agp_sb_get_gtt_total_entries,
+	.install_gatt = agp_i830_install_gatt,
+	.deinstall_gatt = agp_i830_deinstall_gatt,
+	.write_gtt = agp_sb_write_gtt,
+	.install_gtt_pte = agp_sb_install_gtt_pte,
+	.read_gtt_pte = agp_g4x_read_gtt_pte,
+	.read_gtt_pte_paddr = agp_sb_read_gtt_pte_paddr,
+	.set_aperture = agp_i915_set_aperture,
+	.chipset_flush_setup = agp_i810_chipset_flush_setup,
+	.chipset_flush_teardown = agp_i810_chipset_flush_teardown,
+	.chipset_flush = agp_i810_chipset_flush,
 };
 
 /* For adding new devices, devid is the id of the graphics controller
@@ -118,75 +506,232 @@ struct agp_i810_softc {
  */
 static const struct agp_i810_match {
 	int devid;
-	int chiptype;
-	int bridge_offset;
 	char *name;
+	const struct agp_i810_driver *driver;
 } agp_i810_matches[] = {
-	{0x71218086, CHIP_I810, 0x00010000,
-	    "Intel 82810 (i810 GMCH) SVGA controller"},
-	{0x71238086, CHIP_I810, 0x00010000,
-	    "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
-	{0x71258086, CHIP_I810, 0x00010000,
-	    "Intel 82810E (i810E GMCH) SVGA controller"},
-	{0x11328086, CHIP_I810, 0x00020000,
-	    "Intel 82815 (i815 GMCH) SVGA controller"},
-	{0x35778086, CHIP_I830, 0x00020000,
-	    "Intel 82830M (830M GMCH) SVGA controller"},
-	{0x25628086, CHIP_I830, 0x00020000,
-	    "Intel 82845M (845M GMCH) SVGA controller"},
-	{0x35828086, CHIP_I855, 0x00020000,
-	    "Intel 82852/855GM SVGA controller"},
-	{0x25728086, CHIP_I855, 0x00020000,
-	    "Intel 82865G (865G GMCH) SVGA controller"},
-	{0x25828086, CHIP_I915, 0x00020000,
-	    "Intel 82915G (915G GMCH) SVGA controller"},
-	{0x258A8086, CHIP_I915, 0x00020000,
-	    "Intel E7221 SVGA controller"},
-	{0x25928086, CHIP_I915, 0x00020000,
-	    "Intel 82915GM (915GM GMCH) SVGA controller"},
-	{0x27728086, CHIP_I915, 0x00020000,
-	    "Intel 82945G (945G GMCH) SVGA controller"},
-	{0x27A28086, CHIP_I915, 0x00020000,
-	    "Intel 82945GM (945GM GMCH) SVGA controller"},
-	{0x27AE8086, CHIP_I915, 0x00020000,
-	    "Intel 945GME SVGA controller"},
-	{0x29728086, CHIP_I965, 0x00020000,
-	    "Intel 946GZ SVGA controller"},
-	{0x29828086, CHIP_I965, 0x00020000,
-	    "Intel G965 SVGA controller"},
-	{0x29928086, CHIP_I965, 0x00020000,
-	    "Intel Q965 SVGA controller"},
-	{0x29A28086, CHIP_I965, 0x00020000,
-	    "Intel G965 SVGA controller"},
-	{0x29B28086, CHIP_G33, 0x00020000,
-	    "Intel Q35 SVGA controller"},
-	{0x29C28086, CHIP_G33, 0x00020000,
-	    "Intel G33 SVGA controller"},
-	{0x29D28086, CHIP_G33, 0x00020000,
-	    "Intel Q33 SVGA controller"},
-	{0xA0018086, CHIP_IGD, 0x00010000,
-	    "Intel Pineview SVGA controller"},
-	{0xA0118086, CHIP_IGD, 0x00010000,
-	    "Intel Pineview (M) SVGA controller"},
-	{0x2A028086, CHIP_I965, 0x00020000,
-	    "Intel GM965 SVGA controller"},
-	{0x2A128086, CHIP_I965, 0x00020000,
-	    "Intel GME965 SVGA controller"},
-	{0x2A428086, CHIP_G4X, 0x00020000,
-	    "Intel GM45 SVGA controller"},
-	{0x2E028086, CHIP_G4X, 0x00020000,
-	    "Intel Eaglelake SVGA controller"},
-	{0x2E128086, CHIP_G4X, 0x00020000,
-	    "Intel Q45 SVGA controller"},
-	{0x2E228086, CHIP_G4X, 0x00020000,
-	    "Intel G45 SVGA controller"},
-	{0x2E328086, CHIP_G4X, 0x00020000,
-	    "Intel G41 SVGA controller"},
-	{0x00428086, CHIP_G4X, 0x00020000,
-	    "Intel Ironlake (D) SVGA controller"},
-	{0x00468086, CHIP_G4X, 0x00020000,
-	    "Intel Ironlake (M) SVGA controller"},
-	{0, 0, 0, NULL}
+	{
+		.devid = 0x71218086,
+		.name = "Intel 82810 (i810 GMCH) SVGA controller",
+		.driver = &agp_i810_i810_driver
+	},
+	{
+		.devid = 0x71238086,
+		.name = "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller",
+		.driver = &agp_i810_i810_driver
+	},
+	{
+		.devid = 0x71258086,
+		.name = "Intel 82810E (i810E GMCH) SVGA controller",
+		.driver = &agp_i810_i810_driver
+	},
+	{
+		.devid = 0x11328086,
+		.name = "Intel 82815 (i815 GMCH) SVGA controller",
+		.driver = &agp_i810_i815_driver
+	},
+	{
+		.devid = 0x35778086,
+		.name = "Intel 82830M (830M GMCH) SVGA controller",
+		.driver = &agp_i810_i830_driver
+	},
+	{
+		.devid = 0x25628086,
+		.name = "Intel 82845M (845M GMCH) SVGA controller",
+		.driver = &agp_i810_i830_driver
+	},
+	{
+		.devid = 0x35828086,
+		.name = "Intel 82852/855GM SVGA controller",
+		.driver = &agp_i810_i855_driver
+	},
+	{
+		.devid = 0x25728086,
+		.name = "Intel 82865G (865G GMCH) SVGA controller",
+		.driver = &agp_i810_i865_driver
+	},
+	{
+		.devid = 0x25828086,
+		.name = "Intel 82915G (915G GMCH) SVGA controller",
+		.driver = &agp_i810_i915_driver
+	},
+	{
+		.devid = 0x258A8086,
+		.name = "Intel E7221 SVGA controller",
+		.driver = &agp_i810_i915_driver
+	},
+	{
+		.devid = 0x25928086,
+		.name = "Intel 82915GM (915GM GMCH) SVGA controller",
+		.driver = &agp_i810_i915_driver
+	},
+	{
+		.devid = 0x27728086,
+		.name = "Intel 82945G (945G GMCH) SVGA controller",
+		.driver = &agp_i810_i915_driver
+	},
+	{
+		.devid = 0x27A28086,
+		.name = "Intel 82945GM (945GM GMCH) SVGA controller",
+		.driver = &agp_i810_i915_driver
+	},
+	{
+		.devid = 0x27AE8086,
+		.name = "Intel 945GME SVGA controller",
+		.driver = &agp_i810_i915_driver
+	},
+	{
+		.devid = 0x29728086,
+		.name = "Intel 946GZ SVGA controller",
+		.driver = &agp_i810_g965_driver
+	},
+	{
+		.devid = 0x29828086,
+		.name = "Intel G965 SVGA controller",
+		.driver = &agp_i810_g965_driver
+	},
+	{
+		.devid = 0x29928086,
+		.name = "Intel Q965 SVGA controller",
+		.driver = &agp_i810_g965_driver
+	},
+	{
+		.devid = 0x29A28086,
+		.name = "Intel G965 SVGA controller",
+		.driver = &agp_i810_g965_driver
+	},
+	{
+		.devid = 0x29B28086,
+		.name = "Intel Q35 SVGA controller",
+		.driver = &agp_i810_g33_driver
+	},
+	{
+		.devid = 0x29C28086,
+		.name = "Intel G33 SVGA controller",
+		.driver = &agp_i810_g33_driver
+	},
+	{
+		.devid = 0x29D28086,
+		.name = "Intel Q33 SVGA controller",
+		.driver = &agp_i810_g33_driver
+	},
+	{
+		.devid = 0xA0018086,
+		.name = "Intel Pineview SVGA controller",
+		.driver = &agp_i810_igd_driver
+	},
+	{
+		.devid = 0xA0118086,
+		.name = "Intel Pineview (M) SVGA controller",
+		.driver = &agp_i810_igd_driver
+	},
+	{
+		.devid = 0x2A028086,
+		.name = "Intel GM965 SVGA controller",
+		.driver = &agp_i810_g965_driver
+	},
+	{
+		.devid = 0x2A128086,
+		.name = "Intel GME965 SVGA controller",
+		.driver = &agp_i810_g965_driver
+	},
+	{
+		.devid = 0x2A428086,
+		.name = "Intel GM45 SVGA controller",
+		.driver = &agp_i810_g4x_driver
+	},
+	{
+		.devid = 0x2E028086,
+		.name = "Intel Eaglelake SVGA controller",
+		.driver = &agp_i810_g4x_driver
+	},
+	{
+		.devid = 0x2E128086,
+		.name = "Intel Q45 SVGA controller",
+		.driver = &agp_i810_g4x_driver
+	},
+	{
+		.devid = 0x2E228086,
+		.name = "Intel G45 SVGA controller",
+		.driver = &agp_i810_g4x_driver
+	},
+	{
+		.devid = 0x2E328086,
+		.name = "Intel G41 SVGA controller",
+		.driver = &agp_i810_g4x_driver
+	},
+	{
+		.devid = 0x00428086,
+		.name = "Intel Ironlake (D) SVGA controller",
+		.driver = &agp_i810_g4x_driver
+	},
+	{
+		.devid = 0x00468086,
+		.name = "Intel Ironlake (M) SVGA controller",
+		.driver = &agp_i810_g4x_driver
+	},
+	{
+		.devid = 0x01028086,
+		.name = "SandyBridge desktop GT1 IG",
+		.driver = &agp_i810_sb_driver
+	},
+	{
+		.devid = 0x01128086,
+		.name = "SandyBridge desktop GT2 IG",
+		.driver = &agp_i810_sb_driver
+	},
+	{
+		.devid = 0x01228086,
+		.name = "SandyBridge desktop GT2+ IG",
+		.driver = &agp_i810_sb_driver
+	},
+	{
+		.devid = 0x01068086,
+		.name = "SandyBridge mobile GT1 IG",
+		.driver = &agp_i810_sb_driver
+	},
+	{
+		.devid = 0x01168086,
+		.name = "SandyBridge mobile GT2 IG",
+		.driver = &agp_i810_sb_driver
+	},
+	{
+		.devid = 0x01268086,
+		.name = "SandyBridge mobile GT2+ IG",
+		.driver = &agp_i810_sb_driver
+	},
+	{
+		.devid = 0x01088086,
+		.name = "SandyBridge server IG",
+		.driver = &agp_i810_sb_driver
+	},
+	{
+		.devid = 0x01528086,
+		.name = "IvyBridge desktop GT1 IG",
+		.driver = &agp_i810_sb_driver
+	},
+	{
+		.devid = 0x01628086,
+		.name = "IvyBridge desktop GT2 IG",
+		.driver = &agp_i810_sb_driver
+	},
+	{
+		.devid = 0x01568086,
+		.name = "IvyBridge mobile GT1 IG",
+		.driver = &agp_i810_sb_driver
+	},
+	{
+		.devid = 0x01668086,
+		.name = "IvyBridge mobile GT2 IG",
+		.driver = &agp_i810_sb_driver
+	},
+	{
+		.devid = 0x015a8086,
+		.name = "IvyBridge server GT1 IG",
+		.driver = &agp_i810_sb_driver
+	},
+	{
+		.devid = 0,
+	}
 };
 
 static const struct agp_i810_match*
@@ -196,17 +741,17 @@ agp_i810_match(device_t dev)
 
 	if (pci_get_class(dev) != PCIC_DISPLAY
 	    || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
-		return NULL;
+		return (NULL);
 
 	devid = pci_get_devid(dev);
 	for (i = 0; agp_i810_matches[i].devid != 0; i++) {
 		if (agp_i810_matches[i].devid == devid)
-		    break;
+			break;
 	}
 	if (agp_i810_matches[i].devid == 0)
-		return NULL;
+		return (NULL);
 	else
-		return &agp_i810_matches[i];
+		return (&agp_i810_matches[i]);
 }
 
 /*
@@ -215,28 +760,8 @@ agp_i810_match(device_t dev)
 static device_t
 agp_i810_find_bridge(device_t dev)
 {
-	device_t *children, child;
-	int nchildren, i;
-	u_int32_t devid;
-	const struct agp_i810_match *match;
-  
-	match = agp_i810_match(dev);
-	devid = match->devid - match->bridge_offset;
 
-	if (device_get_children(device_get_parent(device_get_parent(dev)),
-	    &children, &nchildren))
-		return 0;
-
-	for (i = 0; i < nchildren; i++) {
-		child = children[i];
-
-		if (pci_get_devid(child) == devid) {
-			free(children, M_TEMP);
-			return child;
-		}
-	}
-	free(children, M_TEMP);
-	return 0;
+	return (pci_find_dbsf(0, 0, 0, 0));
 }
 
 static void
@@ -249,92 +774,116 @@ agp_i810_identify(driver_t *driver, devi
 }
 
 static int
+agp_i810_check_active(device_t bridge_dev)
+{
+	u_int8_t smram;
+
+	smram = pci_read_config(bridge_dev, AGP_I810_SMRAM, 1);
+	if ((smram & AGP_I810_SMRAM_GMS) == AGP_I810_SMRAM_GMS_DISABLED)
+		return (ENXIO);
+	return (0);
+}
+
+static int
+agp_i830_check_active(device_t bridge_dev)
+{
+	int gcc1;
+
+	gcc1 = pci_read_config(bridge_dev, AGP_I830_GCC1, 1);
+	if ((gcc1 & AGP_I830_GCC1_DEV2) == AGP_I830_GCC1_DEV2_DISABLED)
+		return (ENXIO);
+	return (0);
+}
+
+static int
+agp_i915_check_active(device_t bridge_dev)
+{
+	int deven;
+
+	deven = pci_read_config(bridge_dev, AGP_I915_DEVEN, 4);
+	if ((deven & AGP_I915_DEVEN_D2F0) == AGP_I915_DEVEN_D2F0_DISABLED)
+		return (ENXIO);
+	return (0);
+}
+
+static int
+agp_sb_check_active(device_t bridge_dev)
+{
+	int deven;
+
+	deven = pci_read_config(bridge_dev, AGP_I915_DEVEN, 4);
+	if ((deven & AGP_SB_DEVEN_D2EN) == AGP_SB_DEVEN_D2EN_DISABLED)
+		return (ENXIO);
+	return (0);
+}
+
+static void
+agp_82852_set_desc(device_t dev, const struct agp_i810_match *match)
+{
+
+	switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
+	case AGP_I855_GME:
+		device_set_desc(dev,
+		    "Intel 82855GME (855GME GMCH) SVGA controller");
+		break;
+	case AGP_I855_GM:
+		device_set_desc(dev,
+		    "Intel 82855GM (855GM GMCH) SVGA controller");
+		break;
+	case AGP_I852_GME:
+		device_set_desc(dev,
+		    "Intel 82852GME (852GME GMCH) SVGA controller");
+		break;
+	case AGP_I852_GM:
+		device_set_desc(dev,
+		    "Intel 82852GM (852GM GMCH) SVGA controller");
+		break;
+	default:
+		device_set_desc(dev,
+		    "Intel 8285xM (85xGM GMCH) SVGA controller");
+		break;
+	}
+}
+
+static void
+agp_i810_set_desc(device_t dev, const struct agp_i810_match *match)
+{
+
+	device_set_desc(dev, match->name);
+}
+
+static int
 agp_i810_probe(device_t dev)
 {
 	device_t bdev;
 	const struct agp_i810_match *match;
-	u_int8_t smram;
-	int gcc1, deven;
+	int err;
 
 	if (resource_disabled("agp", device_get_unit(dev)))
 		return (ENXIO);
 	match = agp_i810_match(dev);
 	if (match == NULL)
-		return ENXIO;
+		return (ENXIO);
 
 	bdev = agp_i810_find_bridge(dev);
-	if (!bdev) {
+	if (bdev == NULL) {
 		if (bootverbose)
 			printf("I810: can't find bridge device\n");
-		return ENXIO;
+		return (ENXIO);
 	}
 
 	/*
 	 * checking whether internal graphics device has been activated.
 	 */
-	switch (match->chiptype) {
-	case CHIP_I810:
-		smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
-		if ((smram & AGP_I810_SMRAM_GMS) ==
-		    AGP_I810_SMRAM_GMS_DISABLED) {
-			if (bootverbose)
-				printf("I810: disabled, not probing\n");
-			return ENXIO;
-		}
-		break;
-	case CHIP_I830:
-	case CHIP_I855:
-		gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
-		if ((gcc1 & AGP_I830_GCC1_DEV2) ==
-		    AGP_I830_GCC1_DEV2_DISABLED) {
-			if (bootverbose)
-				printf("I830: disabled, not probing\n");
-			return ENXIO;
-		}
-		break;
-	case CHIP_I915:
-	case CHIP_I965:
-	case CHIP_G33:
-	case CHIP_IGD:
-	case CHIP_G4X:
-		deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
-		if ((deven & AGP_I915_DEVEN_D2F0) ==
-		    AGP_I915_DEVEN_D2F0_DISABLED) {
-			if (bootverbose)
-				printf("I915: disabled, not probing\n");
-			return ENXIO;
-		}
-		break;
-	}
-
-	if (match->devid == 0x35828086) {
-		switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
-		case AGP_I855_GME:

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***



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