Date: Fri, 20 May 2022 01:10:39 GMT From: "Bjoern A. Zeeb" <bz@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 85eb99f9a471 - main - LinuxKPI: implement pcie_capability_set_word() Message-ID: <202205200110.24K1Ad3I043740@gitrepo.freebsd.org>
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The branch main has been updated by bz: URL: https://cgit.FreeBSD.org/src/commit/?id=85eb99f9a47151f90565a1fb37395b8302c2978c commit 85eb99f9a47151f90565a1fb37395b8302c2978c Author: Bjoern A. Zeeb <bz@FreeBSD.org> AuthorDate: 2022-05-18 22:36:31 +0000 Commit: Bjoern A. Zeeb <bz@FreeBSD.org> CommitDate: 2022-05-20 01:09:08 +0000 LinuxKPI: implement pcie_capability_set_word() Implement pcie_capability_set_word() using the already available read/write functions. Also define the completion timeout disable value to our PCI one. Both needed by a driver update. Sponsored by: The FreeBSD Foundation MFC after: 3 days Reviewed by: manu, hselasky Differential Revision: https://reviews.freebsd.org/D35250 --- sys/compat/linuxkpi/common/include/linux/pci.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/sys/compat/linuxkpi/common/include/linux/pci.h b/sys/compat/linuxkpi/common/include/linux/pci.h index 35a0f70669fb..d87cf51cf173 100644 --- a/sys/compat/linuxkpi/common/include/linux/pci.h +++ b/sys/compat/linuxkpi/common/include/linux/pci.h @@ -129,6 +129,7 @@ MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE +#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ @@ -1141,6 +1142,22 @@ pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); } +static inline int +pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) +{ + int error; + uint16_t v; + + error = pcie_capability_read_word(dev, pos, &v); + if (error != 0) + return (error); + + v |= val; + + error = pcie_capability_write_word(dev, pos, v); + return (error); +} + static inline int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, enum pcie_link_width *width) {
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