Date: Thu, 5 Aug 2010 16:26:54 +0530 From: "Jayachandran C." <c.jayachandran@gmail.com> To: Alan Cox <alc@cs.rice.edu> Cc: "Jayachandran C." <jchandra@freebsd.org>, mips@freebsd.org Subject: Re: svn commit: r210846 - in head/sys/mips: include mips Message-ID: <AANLkTinP7eMNm4yp6T2TTteSvthdgLJOj-ihHrQJ4T49@mail.gmail.com> In-Reply-To: <4C5A569B.9090401@cs.rice.edu> References: <201008041412.o74ECAix092415@svn.freebsd.org> <4C5A569B.9090401@cs.rice.edu>
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On Thu, Aug 5, 2010 at 11:43 AM, Alan Cox <alc@cs.rice.edu> wrote: > Just an observation ... > > Jayachandran C. wrote: >> >> Author: jchandra >> Date: Wed Aug =A04 14:12:09 2010 >> New Revision: 210846 >> URL: http://svn.freebsd.org/changeset/base/210846 >> >> Log: >> =A0Add 3 level page tables for MIPS in n64. >> =A0 =A0- 32 bit compilation will still use old 2 level page tables >> =A0- re-arrange pmap code so that adding another level is easier >> =A0- pmap code for 3 level page tables for n64 >> =A0- update TLB handler to traverse 3 levels in n64 >> =A0 =A0Reviewed by: =A0 =A0 =A0 =A0jmallett >> > > [snip] >> >> =A0- =A0 =A0 =A0 =A0 =A0 =A0 =A0if (pbits !=3D *pte) { >> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (!atomic_cmpset_int((u_= int *)pte, obits, >> pbits)) >> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 goto retry= ; >> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 pmap_update_page(pmap, sva= , pbits); >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* Skip invalid PTEs */ >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (!pte_test(pte, PTE_V)) >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 continue; >> +retry: >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 obits =3D pbits =3D *pte; >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 pa =3D TLBLO_PTE_TO_PA(pbi= ts); >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (page_is_managed(pa) &&= pte_test(&pbits, >> PTE_D)) { >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 m =3D PHYS= _TO_VM_PAGE(pa); >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 vm_page_di= rty(m); >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 m->md.pv_f= lags &=3D ~PV_TABLE_MOD; >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 } >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 pte_clear(&pbits, PTE_D); >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 pte_set(&pbits, PTE_RO); >> + >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (pbits !=3D *pte) { >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (!atomi= c_cmpset_int((u_int *)pte, >> obits, pbits)) >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 goto retry; >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 pmap_updat= e_page(pmap, sva, pbits); >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 } >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0} >> > > MIPS doesn't really need to use atomic_cmpset_int() in situations like th= is > because the software dirty bit emulation in trap.c acquires the pmap lock= . > =A0Atomics like this appear to be a carryover from i386 where the > hardware-managed TLB might concurrently set the modified bit. Then I guess we should be able to use *pte directly, without pbits, obits and the retry loop. Will try this change... Thanks, JC.
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