Date: Wed, 29 Nov 2017 22:22:58 +0000 From: bugzilla-noreply@freebsd.org To: freebsd-arm@FreeBSD.org Subject: [Bug 223977] UBLDR network packets not aligned to DCACHE in ARMv7. Message-ID: <bug-223977-7@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D223977 Bug ID: 223977 Summary: UBLDR network packets not aligned to DCACHE in ARMv7. Product: Base System Version: 11.1-RELEASE Hardware: arm OS: Any Status: New Severity: Affects Some People Priority: --- Component: arm Assignee: freebsd-arm@FreeBSD.org Reporter: parakleta@darkreality.org In the file `sys/boot/uboot/lib/libuboot.h:47` it says: #define PKTALIGN 32 Unfortunately this causes an error "CACHE: Misaligned operation at range [x= xx, xxx]" since this is not enough to aligned to the data cache in ARMv7 cpus (= such as the AM335x). This value should be changed to reflect the setting in U-B= oot of `CONFIG_SYS_CACHELINE_SIZE` which is determined by `SYS_CACHE_SHIFT_X` define in the U-Boot file `arch/arm/Kconfig`. I have temporarily changed the line to: #define PKTALIGN 64 This change may be sufficient given that the block of memory being aligned = is `ETHER_MAX_LEN` in size (so 1518 bytes) this only wastes ~2% storage. This will fail however for CPUs with a CACHELINE_SIZE of 128 (currently only lis= ted as the ThunderX and the Uniphier). --=20 You are receiving this mail because: You are the assignee for the bug.=
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