From nobody Tue Feb 3 14:05:07 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4f54xb6PGpz6PcN4 for ; Tue, 03 Feb 2026 14:05:07 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R13" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4f54xb3ml5z3jjm for ; Tue, 03 Feb 2026 14:05:07 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1770127507; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=C1StSS1kWR11rpy93LNRV6Ga4p/Yd3WLIfXGypWnBk0=; b=ECL65RxoD+AuRk733rDBO1Jks91UoZb/awdyY1tiebU2OzwPDEOKCCSk1c0QfxfD7limsV tYN5snHhSUc43YtZuCVyLPzgX3kEQlGOCcEs6RGGHWEM0wA05AHAuqaoT55vumthH5aybx SAhR/lx0LdThAm8LDKYi5bfJZdwDSejDjypE8/j03uES1oV8BbaPlnY4VfMryUcNSkoFkf uAVQ1IeZWioy6BaQGJtVPHwnPIkEBnTWB3Vzw1mi6iJfBkvX6tlbU232zq97OndTugLFtD mNyMVZVFyQ+d+yZmOVjnDVaituXQbScAuiidp5y91Pa45cnFGXKxrmG5wde0og== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1770127507; a=rsa-sha256; cv=none; b=LafWJcg7tzxreoGQKpoySKdBnoYSzxxdPz7rn/TGWnsJ3ixLwf3uUrnHJHO6uHSn3Cd0Mb Pw7zm8iKvhXVjW5e8x4JUPvI2ur+l4EWz/asRs+hUF5rqD0Hio4SwIfKp7VW/NGaN1dAwe AUP5qsAuVINeobg43MMh4szuzKVVgYvpjhEyiOlTQ95wkPIpEUErkGbyr6qa1L+Djiuzxi GiF4okHFgEoz4PnoxexBGb2GufqdW2CGgJZEx8oMfF6700vfWYn08hS3E6h37W8HbwCrwC NnzrTE1OU5XHFTKXZMMQyjv7YwzgjxHsq71ZL8QS/jAj+Rb9Em201aR2AtTx9w== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1770127507; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=C1StSS1kWR11rpy93LNRV6Ga4p/Yd3WLIfXGypWnBk0=; b=QwwTuT+8LfpZg6gWKjRLlXBUNVtQNQDroNKuhGhvsZ4/eRkHhjA8DZqRtOmtg8QLD5LESR xgwR9reugDHjZwxlQnyEvyasNnCcadQYmah6Cx508zIXizLYyATi6yjD+f/RQBLA2DvIE2 J9esXgW1dcyZIPai8Lm+X/I+kGaSazXD0iGTGLlP9KURIFRObgC/Vhf/3kOkmXwfNTRMFm iofVN2Jc7oLIzkNexqRbf2dgJ7+pl7fQ8EW1NgLZtCdkPfOXVMtOxMMXjmIi/ILBOo+QRV muqfvgC7XL/1roOqDQkNN5X+XfvuCiMG7hlE68qPSISUi5mhk+w/ukiWzZPw8w== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4f54xb3K5rz1M2 for ; Tue, 03 Feb 2026 14:05:07 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 39ac0 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Tue, 03 Feb 2026 14:05:07 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Olivier Certner Subject: git: 9ae367d11de8 - main - hwpstate_amd(4): Rename CPPC register macros List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: olce X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 9ae367d11de8abbdf53884836c9ba30908c5c8db Auto-Submitted: auto-generated Date: Tue, 03 Feb 2026 14:05:07 +0000 Message-Id: <69820093.39ac0.437a9c73@gitrepo.freebsd.org> The branch main has been updated by olce: URL: https://cgit.FreeBSD.org/src/commit/?id=9ae367d11de8abbdf53884836c9ba30908c5c8db commit 9ae367d11de8abbdf53884836c9ba30908c5c8db Author: Olivier Certner AuthorDate: 2026-01-29 09:08:47 +0000 Commit: Olivier Certner CommitDate: 2026-02-03 14:03:02 +0000 hwpstate_amd(4): Rename CPPC register macros To be closer to AMD's official terminology, except for the "Lowest Non-Linear Performance" field which we label as 'EFFICIENT_PERF' closer to Intel's ("Most Efficient Performance"), and to clear possible confusion. No functional change (intended). Reviewed by: aokblast Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D54998 --- sys/x86/cpufreq/hwpstate_amd.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/sys/x86/cpufreq/hwpstate_amd.c b/sys/x86/cpufreq/hwpstate_amd.c index 08c833d1a2dd..d8ad090a6a58 100644 --- a/sys/x86/cpufreq/hwpstate_amd.c +++ b/sys/x86/cpufreq/hwpstate_amd.c @@ -103,12 +103,12 @@ #define AMD_1AH_CUR_FID(msr) ((msr) & 0xFFF) -#define AMD_CPPC_CAPS_1_HIGH_PERF_BITS 0xff000000 +#define AMD_CPPC_CAPS_1_HIGHEST_PERF_BITS 0xff000000 #define AMD_CPPC_CAPS_1_NOMINAL_PERF_BITS 0x00ff0000 -#define AMD_CPPC_CAPS_1_LOW_NONLIN_PERF_BITS 0x0000ff00 -#define AMD_CPPC_CAPS_1_LOW_PERF_BITS 0x000000ff +#define AMD_CPPC_CAPS_1_EFFICIENT_PERF_BITS 0x0000ff00 +#define AMD_CPPC_CAPS_1_LOWEST_PERF_BITS 0x000000ff -#define AMD_CPPC_REQUEST_ENERGY_PERF_BITS 0xff000000 +#define AMD_CPPC_REQUEST_EPP_BITS 0xff000000 #define AMD_CPPC_REQUEST_DES_PERF_BITS 0x00ff0000 #define AMD_CPPC_REQUEST_MIN_PERF_BITS 0x0000ff00 #define AMD_CPPC_REQUEST_MAX_PERF_BITS 0x000000ff @@ -259,13 +259,13 @@ amdhwp_dump_sysctl_handler(SYSCTL_HANDLER_ARGS) data = request.caps; sbuf_printf(sb, "\tHighest Performance: %03ju\n", - BITS_VALUE(AMD_CPPC_CAPS_1_HIGH_PERF_BITS, data)); + BITS_VALUE(AMD_CPPC_CAPS_1_HIGHEST_PERF_BITS, data)); sbuf_printf(sb, "\tGuaranteed Performance: %03ju\n", BITS_VALUE(AMD_CPPC_CAPS_1_NOMINAL_PERF_BITS, data)); sbuf_printf(sb, "\tEfficient Performance: %03ju\n", - BITS_VALUE(AMD_CPPC_CAPS_1_LOW_NONLIN_PERF_BITS, data)); + BITS_VALUE(AMD_CPPC_CAPS_1_EFFICIENT_PERF_BITS, data)); sbuf_printf(sb, "\tLowest Performance: %03ju\n", - BITS_VALUE(AMD_CPPC_CAPS_1_LOW_PERF_BITS, data)); + BITS_VALUE(AMD_CPPC_CAPS_1_LOWEST_PERF_BITS, data)); sbuf_putc(sb, '\n'); data = request.req; @@ -299,9 +299,9 @@ sysctl_epp_select_per_core(device_t hwp_device, uint32_t val) struct hwpstate_softc *sc; sc = device_get_softc(hwp_device); - if (BITS_VALUE(AMD_CPPC_REQUEST_ENERGY_PERF_BITS, sc->req) == val) + if (BITS_VALUE(AMD_CPPC_REQUEST_EPP_BITS, sc->req) == val) return; - SET_BITS_VALUE(sc->req, AMD_CPPC_REQUEST_ENERGY_PERF_BITS, val); + SET_BITS_VALUE(sc->req, AMD_CPPC_REQUEST_EPP_BITS, val); x86_msr_op(MSR_AMD_CPPC_REQUEST, MSR_OP_RENDEZVOUS_ONE | MSR_OP_WRITE | MSR_OP_CPUID(cpu_get_pcpu(hwp_device)->pc_cpuid), @@ -315,7 +315,7 @@ sysctl_epp_select(SYSCTL_HANDLER_ARGS) devclass_t dc; struct hwpstate_softc *sc; const uint32_t max_energy_perf = - BITS_VALUE(AMD_CPPC_REQUEST_ENERGY_PERF_BITS, (uint64_t)-1); + BITS_VALUE(AMD_CPPC_REQUEST_EPP_BITS, (uint64_t)-1); uint32_t val; int ret = 0; int cpu; @@ -326,7 +326,7 @@ sysctl_epp_select(SYSCTL_HANDLER_ARGS) if (!(sc->flags & PSTATE_CPPC)) return (ENODEV); - val = BITS_VALUE(AMD_CPPC_REQUEST_ENERGY_PERF_BITS, sc->req) * 100 / + val = BITS_VALUE(AMD_CPPC_REQUEST_EPP_BITS, sc->req) * 100 / max_energy_perf; ret = sysctl_handle_int(oidp, &val, 0, req); if (ret != 0 || req->newptr == NULL) @@ -631,11 +631,11 @@ amd_set_autonomous_hwp_cb(void *args) * is the balanced mode. For consistency, we set the same value in AMD's * CPPC driver. */ - SET_BITS_VALUE(sc->req, AMD_CPPC_REQUEST_ENERGY_PERF_BITS, 0x80); + SET_BITS_VALUE(sc->req, AMD_CPPC_REQUEST_EPP_BITS, 0x80); SET_BITS_VALUE(sc->req, AMD_CPPC_REQUEST_MIN_PERF_BITS, - BITS_VALUE(AMD_CPPC_CAPS_1_LOW_PERF_BITS, caps)); + BITS_VALUE(AMD_CPPC_CAPS_1_LOWEST_PERF_BITS, caps)); SET_BITS_VALUE(sc->req, AMD_CPPC_REQUEST_MAX_PERF_BITS, - BITS_VALUE(AMD_CPPC_CAPS_1_HIGH_PERF_BITS, caps)); + BITS_VALUE(AMD_CPPC_CAPS_1_HIGHEST_PERF_BITS, caps)); /* enable autonomous mode by setting desired performance to 0 */ SET_BITS_VALUE(sc->req, AMD_CPPC_REQUEST_DES_PERF_BITS, 0);