From owner-freebsd-questions@FreeBSD.ORG Tue Apr 25 13:48:21 2006 Return-Path: X-Original-To: freebsd-questions@freebsd.org Delivered-To: freebsd-questions@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id B75BD16A401 for ; Tue, 25 Apr 2006 13:48:21 +0000 (UTC) (envelope-from cswiger@mac.com) Received: from pi.codefab.com (pi.codefab.com [199.103.21.227]) by mx1.FreeBSD.org (Postfix) with ESMTP id 2C7B843D46 for ; Tue, 25 Apr 2006 13:48:21 +0000 (GMT) (envelope-from cswiger@mac.com) Received: from localhost (localhost [127.0.0.1]) by pi.codefab.com (Postfix) with ESMTP id 72C715CAF; Tue, 25 Apr 2006 09:48:20 -0400 (EDT) X-Virus-Scanned: amavisd-new at codefab.com Received: from pi.codefab.com ([127.0.0.1]) by localhost (pi.codefab.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hGWEBy2xT1xH; Tue, 25 Apr 2006 09:48:19 -0400 (EDT) Received: from [192.168.1.3] (pool-68-160-235-217.ny325.east.verizon.net [68.160.235.217]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by pi.codefab.com (Postfix) with ESMTP id 3C2965C5D; Tue, 25 Apr 2006 09:48:19 -0400 (EDT) Message-ID: <444E28A5.3010902@mac.com> Date: Tue, 25 Apr 2006 09:48:21 -0400 From: Chuck Swiger User-Agent: Thunderbird 1.5.0.2 (Windows/20060308) MIME-Version: 1.0 To: Bill Moran References: <20060424154617.9dc28c94.wmoran@potentialtech.com> <6.0.0.22.2.20060424175443.02927f48@mail.computinginnovations.com> <20060425084752.2453c0f1.wmoran@collaborativefusion.com> <6.0.0.22.2.20060425075227.028aea10@mail.computinginnovations.com> <20060425092526.6fe5efa6.wmoran@collaborativefusion.com> In-Reply-To: <20060425092526.6fe5efa6.wmoran@collaborativefusion.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: freebsd-questions@freebsd.org, Derek Ragona Subject: Re: Purchasing the correct hardware: dual-core intel? Big cache? X-BeenThere: freebsd-questions@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: User questions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Apr 2006 13:48:21 -0000 Bill Moran wrote: [ ... ] >> If you use well optimized applications, you see the larger performance >> gain. Poor optimization causes a CPU to chug along, flushing the CPU cache >> often, and slowing things down considerably. > > I know. That's why I'm so desperately trying to find a way to determine > how often the cache is being invalidated - so I can determine whether > larger cache sizes (such as 8M) are worthwhile. Guys, you're confusing two things: "flushing the pipeline" vs. "L2 cache hit ratio". The former happens when branch prediction/speculative execution goes awry and requires the CPU to clear the pipeline of partially-executed instructions and backtrack to follow the other path. It is related to optimization quality of compilers, but is not related at all to how big your L2 cache is. The size of your L2 cache affects how much data is more local to the CPU than main memory, and increasing it will improve the L2 cache hit ratio, or, equivalently, reduce L2 cache misses. This is affected by some specific compiler optimizations (cf "loop unrolling"), but tends to reflect the specifics of the workload and how much multitasking of different programs you do more than the compiler. -- -Chuck