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From: Sylvestre Gallon <syl@FreeBSD.org>
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Subject: PERFORCE change 162799 for review
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http://perforce.freebsd.org/chv.cgi?CH=162799

Change 162799 by syl@syl_rincewind on 2009/05/26 19:16:00

	at91sam926x doesn't have the rm9200 st controller, but has watchdog
	       and pit controllers (Programmable Interrupt Timer instead). This 
	       commit imports a driver for the pit and the wdt. It also adds these 
	       two drivers to cpu_devs and enables the dbgu and the 3 uarts 
	       controllers.

Affected files ...

.. //depot/projects/soc2009/syl_usb/src/sys/arm/at91/at91_pit.c#1 add
.. //depot/projects/soc2009/syl_usb/src/sys/arm/at91/at91_pitreg.h#1 add
.. //depot/projects/soc2009/syl_usb/src/sys/arm/at91/at91_wdt.c#1 add
.. //depot/projects/soc2009/syl_usb/src/sys/arm/at91/at91_wdtreg.h#1 add
.. //depot/projects/soc2009/syl_usb/src/sys/arm/at91/files.at91#4 edit
.. //depot/projects/soc2009/syl_usb/src/sys/arm/at91/soc_at91sam9261.c#4 edit

Differences ...

==== //depot/projects/soc2009/syl_usb/src/sys/arm/at91/files.at91#4 (text) ====

@@ -4,7 +4,9 @@
 arm/at91/at91_machdep.c		standard
 arm/at91/at91.c			standard
 arm/at91/at91_cfata.c		optional	at91_cfata
-arm/at91/at91_st.c		standard
+arm/at91/at91_st.c		optional	at91rm9200
+arm/at91/at91_pit.c		optional	at91sam9261
+arm/at91/at91_wdt.c		optional	at91sam9261
 arm/at91/at91_mci.c		optional	at91_mci
 arm/at91/at91_pio.c		standard
 arm/at91/at91_pmc.c		standard

==== //depot/projects/soc2009/syl_usb/src/sys/arm/at91/soc_at91sam9261.c#4 (text+ko) ====

@@ -132,6 +132,16 @@
 {
 	/* PIO need to be check */
 	{
+		"at91_pit", 0,
+		AT91SAM9261_BASE, AT91SAM9261_PIT_BASE, AT91SAM9261_PIT_SIZE,
+		AT91SAM9261_IRQ_SYSTEM
+	},
+	{
+		"at91_wdt", 0,
+		AT91SAM9261_BASE, AT91SAM9261_WDT_BASE, AT91SAM9261_WDT_SIZE,
+		AT91SAM9261_IRQ_SYSTEM
+	},
+	{
 		"at91_udp", 0,
 		AT91SAM9261_BASE + AT91SAM9261_UDP_BASE, AT91SAM9261_UDP_SIZE,
 		AT91SAM9261_IRQ_UDP, AT91SAM9261_IRQ_PIOB
@@ -141,6 +151,26 @@
 		AT91SAM9261_OHCI_BASE, AT91SAM9261_OHCI_SIZE,
 		AT91SAM9261_IRQ_UHP
 	},
+	{
+		"uart", 0,
+		AT91SAM9261_BASE, AT91SAM9261_DBGU_BASE, AT91SAM9261_DBGU_SIZE,
+		AT91SAM9261_IRQ_SYSTEM
+	},
+	{
+		"uart", 1,
+		AT91SAM9261_BASE, AT91SAM9261_USART0_BASE, AT91SAM9261_USART_SIZE,
+		AT91SAM9261_IRQ_USART0
+	},
+	{
+		"uart", 2,
+		AT91SAM9261_BASE, AT91SAM9261_USART1_BASE, AT91SAM9261_USART_SIZE,
+		AT91SAM9261_IRQ_USART1
+	},
+	{
+		"uart", 3,
+		AT91SAM9261_BASE, AT91SAM9261_USART2_BASE, AT91SAM9261_USART_SIZE,
+		AT91SAM9261_IRQ_USART2
+	},
 	{	0, 0, 0, 0, 0 }
 };