From owner-freebsd-arm@FreeBSD.ORG Thu Sep 4 14:00:10 2008 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id E53FB10656A3 for ; Thu, 4 Sep 2008 14:00:10 +0000 (UTC) (envelope-from raj@semihalf.com) Received: from semihalf.com (semihalf.com [206.130.101.55]) by mx1.freebsd.org (Postfix) with ESMTP id B10358FC12 for ; Thu, 4 Sep 2008 14:00:10 +0000 (UTC) (envelope-from raj@semihalf.com) Received: from mail.semihalf.com (mail.semihalf.com [83.15.139.206]) by semihalf.com (8.13.1/8.13.1) with ESMTP id m84De5ow009743; Thu, 4 Sep 2008 07:40:07 -0600 Message-ID: <48BFE533.7010602@semihalf.com> Date: Thu, 04 Sep 2008 15:40:03 +0200 From: Rafal Jaworowski Organization: Semihalf MIME-Version: 1.0 To: Olivier Houchard , "M. Warner Losh" , Sam Leffler Content-Type: text/plain; charset=ISO-8859-2 Content-Transfer-Encoding: 7bit Cc: freebsd-arm@freebsd.org Subject: ARM interrupts fixes X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 04 Sep 2008 14:00:11 -0000 Hi, Please review the following changes around interrupts handling in ARM. We already started discussing these items with Olivier some time ago: 1. http://people.freebsd.org/~raj/patches/arm/intr-fixes.diff At the moment nexus_setup_intr() attempts to set up a number of IRQs in one take, calling arm_setup_irqhandler() in loop. This is bogus, as there's just one cookie given from the caller and it is overwritten in each iteration so that only the last handler's cookie value prevails... This patch removes such behaviour, however there's one [mis]user of the old approach i.e. the IXP425 qmgr, which needs adjustments too, see p.2. Apart from style fixes, another problem which is corrected in this patch is the unmasking the IRQ source in the PIC after the last handler has been removed from list. 2. http://people.freebsd.org/~raj/patches/arm/sys-arm-xscale-ixp425.diff This splits handling of the two QMGR interrupts so they are explicitly managed, as typically done in cases when there are a number of physical IRQs used by one driver. I don't have IXP425 hardware and was able to only compile-test it, so any help with real h/w testing would be appreciated. Let me know your comments. Rafal