Date: Wed, 25 Jul 2012 00:21:16 +0000 (UTC) From: Neel Natu <neel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r238758 - in projects/bhyve/sys: amd64/vmm/intel x86/include Message-ID: <201207250021.q6P0LG65090083@svn.freebsd.org>
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Author: neel Date: Wed Jul 25 00:21:16 2012 New Revision: 238758 URL: http://svn.freebsd.org/changeset/base/238758 Log: Verify that VMX operation has been enabled by BIOS before executing the VMXON instruction. Reported by "s vas" on freebsd-virtualization@ Modified: projects/bhyve/sys/amd64/vmm/intel/vmx.c projects/bhyve/sys/x86/include/specialreg.h Modified: projects/bhyve/sys/amd64/vmm/intel/vmx.c ============================================================================== --- projects/bhyve/sys/amd64/vmm/intel/vmx.c Tue Jul 24 22:48:12 2012 (r238757) +++ projects/bhyve/sys/amd64/vmm/intel/vmx.c Wed Jul 25 00:21:16 2012 (r238758) @@ -427,7 +427,7 @@ static int vmx_init(void) { int error; - uint64_t fixed0, fixed1; + uint64_t fixed0, fixed1, feature_control; uint32_t tmp; /* CPUID.1:ECX[bit 5] must be 1 for processor to support VMX */ @@ -436,6 +436,16 @@ vmx_init(void) return (ENXIO); } + /* + * Verify that MSR_IA32_FEATURE_CONTROL lock and VMXON enable bits + * are set (bits 0 and 2 respectively). + */ + feature_control = rdmsr(MSR_IA32_FEATURE_CONTROL); + if ((feature_control & 0x5) != 0x5) { + printf("vmx_init: VMX operation disabled by BIOS\n"); + return (ENXIO); + } + /* Check support for primary processor-based VM-execution controls */ error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS, MSR_VMX_TRUE_PROCBASED_CTLS, Modified: projects/bhyve/sys/x86/include/specialreg.h ============================================================================== --- projects/bhyve/sys/x86/include/specialreg.h Tue Jul 24 22:48:12 2012 (r238757) +++ projects/bhyve/sys/x86/include/specialreg.h Wed Jul 25 00:21:16 2012 (r238758) @@ -294,6 +294,7 @@ #define MSR_APICBASE 0x01b #define MSR_EBL_CR_POWERON 0x02a #define MSR_TEST_CTL 0x033 +#define MSR_IA32_FEATURE_CONTROL 0x03a #define MSR_BIOS_UPDT_TRIG 0x079 #define MSR_BBL_CR_D0 0x088 #define MSR_BBL_CR_D1 0x089
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