From owner-svn-src-head@freebsd.org Thu Nov 5 00:52:53 2020 Return-Path: Delivered-To: svn-src-head@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id ED8BB46AC78; Thu, 5 Nov 2020 00:52:53 +0000 (UTC) (envelope-from mhorne@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4CRQ3n62KYz4VpG; Thu, 5 Nov 2020 00:52:53 +0000 (UTC) (envelope-from mhorne@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id B07C716791; Thu, 5 Nov 2020 00:52:53 +0000 (UTC) (envelope-from mhorne@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 0A50qrnT013154; Thu, 5 Nov 2020 00:52:53 GMT (envelope-from mhorne@FreeBSD.org) Received: (from mhorne@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 0A50qrDQ013152; Thu, 5 Nov 2020 00:52:53 GMT (envelope-from mhorne@FreeBSD.org) Message-Id: <202011050052.0A50qrDQ013152@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mhorne set sender to mhorne@FreeBSD.org using -f From: Mitchell Horne Date: Thu, 5 Nov 2020 00:52:53 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r367356 - head/sys/riscv/riscv X-SVN-Group: head X-SVN-Commit-Author: mhorne X-SVN-Commit-Paths: head/sys/riscv/riscv X-SVN-Commit-Revision: 367356 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.33 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Nov 2020 00:52:54 -0000 Author: mhorne Date: Thu Nov 5 00:52:52 2020 New Revision: 367356 URL: https://svnweb.freebsd.org/changeset/base/367356 Log: riscv: set kernel_pmap hart mask more precisely In pmap_bootstrap(), we fill kernel_pmap->pm_active since it is invariably active on all harts. However, this marks it as active even for harts that don't exist in the system, which can cause issue when the mask is passed to the SBI firmware via sbi_remote_sfence_vma(). Specifically, the SBI spec allows SBI_ERR_INVALID_PARAM to be returned when an invalid hart is set in the mask. The latest version of OpenSBI does not have this issue, but v0.6 does, and this is triggering a recently added KASSERT in CI. Switch to only setting bits in pm_active for harts that enter the system. Reported by: Jenkins Reviewed by: markj Differential Revision: https://reviews.freebsd.org/D27080 Modified: head/sys/riscv/riscv/mp_machdep.c head/sys/riscv/riscv/pmap.c Modified: head/sys/riscv/riscv/mp_machdep.c ============================================================================== --- head/sys/riscv/riscv/mp_machdep.c Wed Nov 4 23:29:27 2020 (r367355) +++ head/sys/riscv/riscv/mp_machdep.c Thu Nov 5 00:52:52 2020 (r367356) @@ -46,6 +46,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include @@ -265,6 +266,9 @@ init_secondary(uint64_t hart) /* Enable external (PLIC) interrupts */ csr_set(sie, SIE_SEIE); + + /* Activate this hart in the kernel pmap. */ + CPU_SET_ATOMIC(hart, &kernel_pmap->pm_active); /* Activate process 0's pmap. */ pmap_activate_boot(vmspace_pmap(proc0.p_vmspace)); Modified: head/sys/riscv/riscv/pmap.c ============================================================================== --- head/sys/riscv/riscv/pmap.c Wed Nov 4 23:29:27 2020 (r367355) +++ head/sys/riscv/riscv/pmap.c Thu Nov 5 00:52:52 2020 (r367356) @@ -573,7 +573,12 @@ pmap_bootstrap(vm_offset_t l1pt, vm_paddr_t kernstart, rw_init(&pvh_global_lock, "pmap pv global"); - CPU_FILL(&kernel_pmap->pm_active); + /* + * Set the current CPU as active in the kernel pmap. Secondary cores + * will add themselves later in init_secondary(). The SBI firmware + * may rely on this mask being precise, so CPU_FILL() is not used. + */ + CPU_SET(PCPU_GET(hart), &kernel_pmap->pm_active); /* Assume the address we were loaded to is a valid physical address. */ min_pa = max_pa = kernstart;