Date: Tue, 6 Sep 2016 14:59:14 +0000 (UTC) From: Wojciech Macek <wma@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r305477 - in head/sys/contrib/alpine-hal: . eth eth/eth Message-ID: <201609061459.u86ExElr083698@repo.freebsd.org>
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Author: wma Date: Tue Sep 6 14:59:13 2016 New Revision: 305477 URL: https://svnweb.freebsd.org/changeset/base/305477 Log: Update Annapurna Alpine HAL to a newer version. HAL version: 2.7a Import from vendor-sys, r305475 Added: head/sys/contrib/alpine-hal/al_hal_serdes_25g.c (contents, props changed) head/sys/contrib/alpine-hal/al_hal_serdes_25g.h (contents, props changed) head/sys/contrib/alpine-hal/al_hal_serdes_25g_internal_regs.h (contents, props changed) head/sys/contrib/alpine-hal/al_hal_serdes_25g_regs.h (contents, props changed) head/sys/contrib/alpine-hal/al_hal_serdes_hssp.h (contents, props changed) head/sys/contrib/alpine-hal/al_hal_serdes_hssp_internal_regs.h (contents, props changed) head/sys/contrib/alpine-hal/al_hal_serdes_hssp_regs.h (contents, props changed) head/sys/contrib/alpine-hal/al_hal_serdes_interface.h (contents, props changed) head/sys/contrib/alpine-hal/al_serdes.c (contents, props changed) head/sys/contrib/alpine-hal/al_serdes.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_common.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_iofic.c (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_iofic.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_iofic_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_nb_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_pbs_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_pcie.c (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_pcie.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_pcie_axi_reg.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_pcie_interrupts.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_pcie_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_pcie_w_reg.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_plat_services.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_plat_types.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_reg_utils.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_serdes.c (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_serdes.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_serdes_25g.c (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_serdes_25g.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_serdes_25g_internal_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_serdes_25g_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_serdes_hssp.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_serdes_hssp_internal_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_serdes_hssp_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_serdes_interface.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_serdes_internal_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_serdes_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_types.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_udma.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_udma_config.c (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_udma_config.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_udma_debug.c (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_udma_debug.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_udma_iofic.c (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_udma_iofic.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_udma_iofic_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_udma_main.c (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_udma_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_udma_regs_gen.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_udma_regs_m2s.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_udma_regs_s2m.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_hal_unit_adapter_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/al_serdes.c (contents, props changed) head/sys/contrib/alpine-hal/eth/al_serdes.h (contents, props changed) head/sys/contrib/alpine-hal/eth/eth/ head/sys/contrib/alpine-hal/eth/eth/al_hal_an_lt_wrapper_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/eth/al_hal_eth.h (contents, props changed) head/sys/contrib/alpine-hal/eth/eth/al_hal_eth_alu.h (contents, props changed) head/sys/contrib/alpine-hal/eth/eth/al_hal_eth_ec_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/eth/al_hal_eth_kr.c (contents, props changed) head/sys/contrib/alpine-hal/eth/eth/al_hal_eth_kr.h (contents, props changed) head/sys/contrib/alpine-hal/eth/eth/al_hal_eth_mac_regs.h (contents, props changed) head/sys/contrib/alpine-hal/eth/eth/al_hal_eth_main.c (contents, props changed) Modified: head/sys/contrib/alpine-hal/al_hal_iofic.c head/sys/contrib/alpine-hal/al_hal_iofic.h head/sys/contrib/alpine-hal/al_hal_iofic_regs.h head/sys/contrib/alpine-hal/al_hal_nb_regs.h head/sys/contrib/alpine-hal/al_hal_pbs_regs.h head/sys/contrib/alpine-hal/al_hal_pcie.c head/sys/contrib/alpine-hal/al_hal_pcie.h head/sys/contrib/alpine-hal/al_hal_pcie_axi_reg.h head/sys/contrib/alpine-hal/al_hal_pcie_interrupts.h head/sys/contrib/alpine-hal/al_hal_pcie_regs.h head/sys/contrib/alpine-hal/al_hal_pcie_w_reg.h head/sys/contrib/alpine-hal/al_hal_plat_services.h head/sys/contrib/alpine-hal/al_hal_plat_types.h head/sys/contrib/alpine-hal/al_hal_reg_utils.h head/sys/contrib/alpine-hal/al_hal_serdes.c head/sys/contrib/alpine-hal/al_hal_serdes.h head/sys/contrib/alpine-hal/al_hal_udma.h head/sys/contrib/alpine-hal/al_hal_udma_config.c head/sys/contrib/alpine-hal/al_hal_udma_config.h head/sys/contrib/alpine-hal/al_hal_udma_debug.c head/sys/contrib/alpine-hal/al_hal_udma_iofic.h head/sys/contrib/alpine-hal/al_hal_udma_main.c head/sys/contrib/alpine-hal/al_hal_udma_regs_gen.h head/sys/contrib/alpine-hal/al_hal_unit_adapter_regs.h head/sys/contrib/alpine-hal/eth/al_hal_eth.h head/sys/contrib/alpine-hal/eth/al_hal_eth_mac_regs.h head/sys/contrib/alpine-hal/eth/al_hal_eth_main.c Modified: head/sys/contrib/alpine-hal/al_hal_iofic.c ============================================================================== --- head/sys/contrib/alpine-hal/al_hal_iofic.c Tue Sep 6 14:52:14 2016 (r305476) +++ head/sys/contrib/alpine-hal/al_hal_iofic.c Tue Sep 6 14:59:13 2016 (r305477) @@ -129,10 +129,10 @@ int al_iofic_msix_moder_interval_config( } /* - * configure the vmid attributes for a given msix vector. + * configure the target-id attributes for a given msix vector. */ -int al_iofic_msix_vmid_attributes_config(void __iomem *regs_base, int group, - uint8_t vector, uint32_t vmid, uint8_t vmid_en) +int al_iofic_msix_tgtid_attributes_config(void __iomem *regs_base, int group, + uint8_t vector, uint32_t tgtid, uint8_t tgtid_en) { struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base); uint32_t reg = 0; @@ -141,14 +141,14 @@ int al_iofic_msix_vmid_attributes_config al_assert(group < AL_IOFIC_MAX_GROUPS); AL_REG_FIELD_SET(reg, - INT_MSIX_VMID_MASK, - INT_MSIX_VMID_SHIFT, - vmid); + INT_MSIX_TGTID_MASK, + INT_MSIX_TGTID_SHIFT, + tgtid); AL_REG_BIT_VAL_SET(reg, - INT_MSIX_VMID_EN_SHIFT, - vmid_en); + INT_MSIX_TGTID_EN_SHIFT, + tgtid_en); - al_reg_write32(®s->grp_int_mod[group][vector].grp_int_vmid_reg, reg); + al_reg_write32(®s->grp_int_mod[group][vector].grp_int_tgtid_reg, reg); return 0; } Modified: head/sys/contrib/alpine-hal/al_hal_iofic.h ============================================================================== --- head/sys/contrib/alpine-hal/al_hal_iofic.h Tue Sep 6 14:52:14 2016 (r305476) +++ head/sys/contrib/alpine-hal/al_hal_iofic.h Tue Sep 6 14:59:13 2016 (r305477) @@ -117,17 +117,17 @@ int al_iofic_msix_moder_interval_config( uint8_t vector, uint8_t interval); /** -* configure the vmid attributes for a given msix vector. +* configure the tgtid attributes for a given msix vector. * * @param group the interrupt group * @param vector index -* @param vmid the vmid value -* @param vmid_en take vmid from the intc +* @param tgtid the target-id value +* @param tgtid_en take target-id from the intc * * @return 0 on success. -EINVAL otherwise. */ -int al_iofic_msix_vmid_attributes_config(void __iomem *regs_base, int group, - uint8_t vector, uint32_t vmid, uint8_t vmid_en); +int al_iofic_msix_tgtid_attributes_config(void __iomem *regs_base, int group, + uint8_t vector, uint32_t tgtid, uint8_t tgtid_en); /** * return the offset of the unmask register for a given group. Modified: head/sys/contrib/alpine-hal/al_hal_iofic_regs.h ============================================================================== --- head/sys/contrib/alpine-hal/al_hal_iofic_regs.h Tue Sep 6 14:52:14 2016 (r305476) +++ head/sys/contrib/alpine-hal/al_hal_iofic_regs.h Tue Sep 6 14:59:13 2016 (r305477) @@ -66,7 +66,7 @@ struct al_iofic_grp_ctrl { struct al_iofic_grp_mod { uint32_t grp_int_mod_reg; /* Interrupt moderation registerDedicated moderation in ... */ - uint32_t grp_int_vmid_reg; + uint32_t grp_int_tgtid_reg; }; struct al_iofic_regs { @@ -109,12 +109,12 @@ struct al_iofic_regs { #define INT_MOD_INTV_MASK 0x000000FF #define INT_MOD_INTV_SHIFT 0 -/**** grp_int_vmid_reg register ****/ -/* Interrupt vmid value registerDedicated reg ... */ -#define INT_MSIX_VMID_MASK 0x0000FFFF -#define INT_MSIX_VMID_SHIFT 0 -/* Interrupt vmid_en value registerDedicated reg ... */ -#define INT_MSIX_VMID_EN_SHIFT 31 +/**** grp_int_tgtid_reg register ****/ +/* Interrupt tgtid value registerDedicated reg ... */ +#define INT_MSIX_TGTID_MASK 0x0000FFFF +#define INT_MSIX_TGTID_SHIFT 0 +/* Interrupt tgtid_en value registerDedicated reg ... */ +#define INT_MSIX_TGTID_EN_SHIFT 31 #ifdef __cplusplus } Modified: head/sys/contrib/alpine-hal/al_hal_nb_regs.h ============================================================================== --- head/sys/contrib/alpine-hal/al_hal_nb_regs.h Tue Sep 6 14:52:14 2016 (r305476) +++ head/sys/contrib/alpine-hal/al_hal_nb_regs.h Tue Sep 6 14:59:13 2016 (r305477) @@ -355,7 +355,7 @@ struct al_nb_nb_version { }; struct al_nb_sriov { /* [0x0] */ - uint32_t cpu_vmid[4]; + uint32_t cpu_tgtid[4]; uint32_t rsrvd[4]; }; struct al_nb_dram_channels { @@ -403,7 +403,7 @@ struct al_nb_push_packet { uint32_t pp_config; uint32_t rsrvd_0[3]; /* [0x10] */ - uint32_t pp_ext_awuser; + uint32_t pp_ext_attr; uint32_t rsrvd_1[3]; /* [0x20] */ uint32_t pp_base_low; @@ -411,7 +411,7 @@ struct al_nb_push_packet { uint32_t pp_base_high; uint32_t rsrvd_2[2]; /* [0x30] */ - uint32_t pp_sel_awuser; + uint32_t pp_sel_attr; uint32_t rsrvd[51]; }; @@ -853,8 +853,8 @@ Enables 4k hazard of post-barrier vs pre This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset. */ #define NB_GLOBAL_LGIC_BASE_HIGH_BASE_39_32_MASK 0x000000FF #define NB_GLOBAL_LGIC_BASE_HIGH_BASE_39_32_SHIFT 0 -#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_MASK_PKR 0x00000FFF -#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_SHIFT_PKR 0 +#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_MASK_ALPINE_V2 0x00000FFF +#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_SHIFT_ALPINE_V2 0 /* GIC registers base [31:15]. This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset */ #define NB_GLOBAL_LGIC_BASE_LOW_BASED_31_15_MASK 0xFFFF8000 @@ -1055,9 +1055,9 @@ Other access types are hazard check aga /* Disable counter (wait 1000 NB cycles) before applying PoS enable/disable configuration */ #define NB_GLOBAL_ACF_MISC_POS_CONFIG_CNT_DIS (1 << 14) /* Disable wr spliter A0 bug fixes */ -#define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_M0_MODE (1 << 16) -/* Disable wr spliter PKR bug fixes */ -#define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_A0_MODE (1 << 17) +#define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_V1_M0_MODE (1 << 16) +/* Disable wr spliter ALPINE_V2 bug fixes */ +#define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_V1_A0_MODE (1 << 17) /* Override the address parity calucation for write transactions going to IO-fabric */ #define NB_GLOBAL_ACF_MISC_NB_NIC_AWADDR_PAR_OVRD (1 << 18) /* Override the data parity calucation for write transactions going to IO-fabric */ @@ -1074,7 +1074,7 @@ Other access types are hazard check aga #define NB_GLOBAL_ACF_MISC_CPU_DSB_FLUSH_DIS (1 << 26) /* Enable DMB flush request to NB to SB PoS when barrier is terminted inside the processor cluster */ #define NB_GLOBAL_ACF_MISC_CPU_DMB_FLUSH_DIS (1 << 27) -/* Peakrock only: remap CPU address above 40 bits to Slave Error +/* Alpine V2 only: remap CPU address above 40 bits to Slave Error INTERNAL */ #define NB_GLOBAL_ACF_MISC_ADDR43_40_REMAP_DIS (1 << 28) /* Enable CPU WriteUnique to WriteNoSnoop trasform */ @@ -1586,7 +1586,7 @@ enable - 0x1: Enable interrupt on overfl /* Number of monitored events supported by the PMU. */ #define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_MASK 0x00FC0000 #define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_SHIFT 18 -#define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_SHIFT_ALPINE 19 +#define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_SHIFT_ALPINE_V1 19 /* Number of counters implemented by PMU. */ #define NB_MC_PMU_PMU_CONTROL_NUM_OF_CNTS_MASK 0x0F000000 #define NB_MC_PMU_PMU_CONTROL_NUM_OF_CNTS_SHIFT 24 @@ -1659,6 +1659,9 @@ Note: This field must be changed for lar /* Revision number (Major) */ #define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00 #define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_SHIFT 8 +#define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_VAL_ALPINE_V1 2 +#define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_VAL_ALPINE_V2 3 +#define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_VAL_ALPINE_V3 4 /* Date of release */ #define NB_NB_VERSION_VERSION_DATE_DAY_MASK 0x001F0000 #define NB_NB_VERSION_VERSION_DATE_DAY_SHIFT 16 @@ -1672,10 +1675,10 @@ Note: This field must be changed for lar #define NB_NB_VERSION_VERSION_RESERVED_MASK 0xC0000000 #define NB_NB_VERSION_VERSION_RESERVED_SHIFT 30 -/**** cpu_vmid register ****/ -/* Target VMID */ -#define NB_SRIOV_CPU_VMID_VAL_MASK 0x000000FF -#define NB_SRIOV_CPU_VMID_VAL_SHIFT 0 +/**** cpu_tgtid register ****/ +/* Target-ID */ +#define NB_SRIOV_CPU_TGTID_VAL_MASK 0x000000FF +#define NB_SRIOV_CPU_TGTID_VAL_SHIFT 0 /**** DRAM_0_Control register ****/ /* Controller Idle @@ -1807,7 +1810,7 @@ Parity bits are still generated per tran #define NB_PUSH_PACKET_PP_EXT_AWUSER_AWUSER_SHIFT 0 /**** pp_sel_awuser register ****/ -/* Select whether to use addr[63:48] or PP awmisc as vmid. +/* Select whether to use addr[63:48] or PP awmisc as tgtid. Each bit if set to 1 selects the corresponding address bit. Otherwise, selects the corersponding awmis bit. */ #define NB_PUSH_PACKET_PP_SEL_AWUSER_SEL_MASK 0x0000FFFF #define NB_PUSH_PACKET_PP_SEL_AWUSER_SEL_SHIFT 0 Modified: head/sys/contrib/alpine-hal/al_hal_pbs_regs.h ============================================================================== --- head/sys/contrib/alpine-hal/al_hal_pbs_regs.h Tue Sep 6 14:52:14 2016 (r305476) +++ head/sys/contrib/alpine-hal/al_hal_pbs_regs.h Tue Sep 6 14:59:13 2016 (r305477) @@ -447,11 +447,12 @@ struct al_pbs_target_id_enforcement { }; struct al_pbs_regs { - struct al_pbs_unit unit; /* [0x0] */ -struct al_pbs_low_latency_sram_remap low_latency_sram_remap; -/* [0x250] */ - uint32_t rsrvd_0[88]; - struct al_pbs_target_id_enforcement target_id_enforcement; /* [0x400] */ + struct al_pbs_unit unit; /* [0x0] */ + struct al_pbs_low_latency_sram_remap low_latency_sram_remap; /* [0x250] */ + uint32_t rsrvd_0[24]; + uint32_t iofic_base; /* [0x300] */ + uint32_t rsrvd_1[63]; + struct al_pbs_target_id_enforcement target_id_enforcement; /* [0x400] */ }; @@ -849,50 +850,50 @@ struct al_pbs_low_latency_sram_remap low * 2'b01 - select pcie_b[0] * 2'b10 - select pcie_a[2] */ -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_2_MASK 0x00000003 -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_2_SHIFT 0 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_2_MASK 0x00000003 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_2_SHIFT 0 /* * 2'b01 - select pcie_b[1] * 2'b10 - select pcie_a[3] */ -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_3_MASK 0x00000030 -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_3_SHIFT 4 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_3_MASK 0x00000030 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_3_SHIFT 4 /* * 2'b01 - select pcie_b[0] * 2'b10 - select pcie_a[4] */ -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_4_MASK 0x00000300 -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_4_SHIFT 8 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_4_MASK 0x00000300 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_4_SHIFT 8 /* * 2'b01 - select pcie_b[1] * 2'b10 - select pcie_a[5] */ -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_5_MASK 0x00003000 -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_5_SHIFT 12 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_5_MASK 0x00003000 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_5_SHIFT 12 /* * 2'b01 - select pcie_b[2] * 2'b10 - select pcie_a[6] */ -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_6_MASK 0x00030000 -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_6_SHIFT 16 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_6_MASK 0x00030000 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_6_SHIFT 16 /* * 2'b01 - select pcie_b[3] * 2'b10 - select pcie_a[7] */ -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_7_MASK 0x00300000 -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_7_SHIFT 20 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_7_MASK 0x00300000 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_7_SHIFT 20 /* * 2'b01 - select pcie_d[0] * 2'b10 - select pcie_c[2] */ -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_10_MASK 0x03000000 -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_10_SHIFT 24 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_10_MASK 0x03000000 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_10_SHIFT 24 /* * 2'b01 - select pcie_d[1] * 2'b10 - select pcie_c[3] */ -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_11_MASK 0x30000000 -#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_11_SHIFT 28 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_11_MASK 0x30000000 +#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_11_SHIFT 28 /**** dma_io_master_map register ****/ /* @@ -978,6 +979,14 @@ struct al_pbs_low_latency_sram_remap low #define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_MASK 0x3C000000 #define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_SHIFT 26 +/**** cfg_axi_conf_3 register ****/ +#define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_LOW_MASK 0xFFFF +#define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_LOW_SHIFT 0 +#define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_HI_MASK 0xFF0000 +#define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_HI_SHIFT 16 +#define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_SPI_HI_MASK 0xFF000000 +#define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_SPI_HI_SHIFT 24 + /**** spi_mst_conf_0 register ****/ /* * Sets the SPI master Configuration. For details see the SPI section in the @@ -1137,9 +1146,9 @@ struct al_pbs_low_latency_sram_remap low #define PBS_UNIT_CHIP_ID_DEV_ID_MASK 0xFFFF0000 #define PBS_UNIT_CHIP_ID_DEV_ID_SHIFT 16 -#define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE 0 -#define PBS_UNIT_CHIP_ID_DEV_ID_PEAKROCK 1 -#define PBS_UNIT_CHIP_ID_DEV_ID_COYOTE 2 +#define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE_V1 0 +#define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE_V2 1 +#define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE_V3 2 /**** uart0_conf_status register ****/ /* @@ -1420,56 +1429,56 @@ struct al_pbs_low_latency_sram_remap low * 2'b01 - select sata_b[0] * 2'b10 - select eth_a[0] */ -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_8_MASK 0x00000003 -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_8_SHIFT 0 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_8_MASK 0x00000003 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_8_SHIFT 0 /* * 3'b001 - select sata_b[1] * 3'b010 - select eth_b[0] * 3'b100 - select eth_a[1] */ -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_9_MASK 0x00000070 -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_9_SHIFT 4 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_9_MASK 0x00000070 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_9_SHIFT 4 /* * 3'b001 - select sata_b[2] * 3'b010 - select eth_c[0] * 3'b100 - select eth_a[2] */ -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_10_MASK 0x00000700 -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_10_SHIFT 8 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_10_MASK 0x00000700 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_10_SHIFT 8 /* * 3'b001 - select sata_b[3] * 3'b010 - select eth_d[0] * 3'b100 - select eth_a[3] */ -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_11_MASK 0x00007000 -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_11_SHIFT 12 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_11_MASK 0x00007000 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_11_SHIFT 12 /* * 2'b01 - select eth_a[0] * 2'b10 - select sata_a[0] */ -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_12_MASK 0x00030000 -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_12_SHIFT 16 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_12_MASK 0x00030000 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_12_SHIFT 16 /* * 3'b001 - select eth_b[0] * 3'b010 - select eth_c[1] * 3'b100 - select sata_a[1] */ -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_13_MASK 0x00700000 -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_13_SHIFT 20 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_13_MASK 0x00700000 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_13_SHIFT 20 /* * 3'b001 - select eth_a[0] * 3'b010 - select eth_c[2] * 3'b100 - select sata_a[2] */ -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_14_MASK 0x07000000 -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_14_SHIFT 24 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_14_MASK 0x07000000 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_14_SHIFT 24 /* * 3'b001 - select eth_d[0] * 3'b010 - select eth_c[3] * 3'b100 - select sata_a[3] */ -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_15_MASK 0x70000000 -#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_15_SHIFT 28 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_15_MASK 0x70000000 +#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_15_SHIFT 28 /**** serdes_mux_multi_1 register ****/ /* SerDes one hot mux control. For details see datasheet. */ @@ -1632,62 +1641,62 @@ struct al_pbs_low_latency_sram_remap low * 2'b01 - eth_a[0] from serdes_8 * 2'b10 - eth_a[0] from serdes_14 */ -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_0_MASK 0x00000003 -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_0_SHIFT 0 +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_0_MASK 0x00000003 +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_0_SHIFT 0 /* * 2'b01 - eth_b[0] from serdes_9 * 2'b10 - eth_b[0] from serdes_13 */ -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_B_0_MASK 0x00000030 -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_B_0_SHIFT 4 +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_B_0_MASK 0x00000030 +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_B_0_SHIFT 4 /* * 2'b01 - eth_c[0] from serdes_10 * 2'b10 - eth_c[0] from serdes_12 */ -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_0_MASK 0x00000300 -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_0_SHIFT 8 +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_0_MASK 0x00000300 +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_0_SHIFT 8 /* * 2'b01 - eth_d[0] from serdes_11 * 2'b10 - eth_d[0] from serdes_15 */ -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_D_0_MASK 0x00003000 -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_D_0_SHIFT 12 +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_D_0_MASK 0x00003000 +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_D_0_SHIFT 12 /* which lane's is master clk */ -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_ICK_MASTER_MASK 0x00030000 -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_ICK_MASTER_SHIFT 16 +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_ICK_MASTER_MASK 0x00030000 +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_ICK_MASTER_SHIFT 16 /* which lane's is master clk */ -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_ICK_MASTER_MASK 0x00300000 -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_ICK_MASTER_SHIFT 20 +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_ICK_MASTER_MASK 0x00300000 +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_ICK_MASTER_SHIFT 20 /* enable xlaui on eth a */ -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_XLAUI_ENABLE (1 << 24) +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_XLAUI_ENABLE (1 << 24) /* enable xlaui on eth c */ -#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_XLAUI_ENABLE (1 << 28) +#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_XLAUI_ENABLE (1 << 28) /**** serdes_mux_pcie register ****/ /* * 2'b01 - select pcie_b[0] from serdes 2 * 2'b10 - select pcie_b[0] from serdes 4 */ -#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_0_MASK 0x00000003 -#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_0_SHIFT 0 +#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_B_0_MASK 0x00000003 +#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_B_0_SHIFT 0 /* * 2'b01 - select pcie_b[1] from serdes 3 * 2'b10 - select pcie_b[1] from serdes 5 */ -#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_1_MASK 0x00000030 -#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_1_SHIFT 4 +#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_B_1_MASK 0x00000030 +#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_B_1_SHIFT 4 /* * 2'b01 - select pcie_d[0] from serdes 10 * 2'b10 - select pcie_d[0] from serdes 12 */ -#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_0_MASK 0x00000300 -#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_0_SHIFT 8 +#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_D_0_MASK 0x00000300 +#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_D_0_SHIFT 8 /* * 2'b01 - select pcie_d[1] from serdes 11 * 2'b10 - select pcie_d[1] from serdes 13 */ -#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_1_MASK 0x00003000 -#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_1_SHIFT 12 +#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_D_1_MASK 0x00003000 +#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_D_1_SHIFT 12 /**** serdes_mux_sata register ****/ /* Modified: head/sys/contrib/alpine-hal/al_hal_pcie.c ============================================================================== --- head/sys/contrib/alpine-hal/al_hal_pcie.c Tue Sep 6 14:52:14 2016 (r305476) +++ head/sys/contrib/alpine-hal/al_hal_pcie.c Tue Sep 6 14:59:13 2016 (r305477) @@ -96,6 +96,8 @@ __FBSDID("$FreeBSD$"); #define AL_PCIE_PARSE_LANES(v) (((1 << v) - 1) << \ PCIE_REVX_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_SHIFT) +#define AL_PCIE_FLR_DONE_INTERVAL 10 + /** * Static functions */ @@ -183,10 +185,6 @@ al_pcie_port_link_config( return -EINVAL; } - al_dbg("PCIe %d: link config: max speed gen %d, max lanes %d, reversal %s\n", - pcie_port->port_id, link_params->max_speed, - pcie_port->max_lanes, link_params->enable_reversal? "enable" : "disable"); - al_pcie_port_link_speed_ctrl_set(pcie_port, link_params->max_speed); /* Change Max Payload Size, if needed. @@ -220,12 +218,6 @@ al_pcie_port_link_config( (max_lanes + (max_lanes-1)) << PCIE_PORT_LINK_CTRL_LINK_CAPABLE_SHIFT); - /* TODO: add support for reversal mode */ - if (link_params->enable_reversal) { - al_err("PCIe %d: enabling reversal mode not implemented\n", - pcie_port->port_id); - return -ENOSYS; - } return 0; } @@ -364,12 +356,9 @@ al_pcie_rev_id_get( PBS_UNIT_CHIP_ID_DEV_ID_MASK, PBS_UNIT_CHIP_ID_DEV_ID_SHIFT); - if (chip_id_dev == PBS_UNIT_CHIP_ID_DEV_ID_ALPINE) { - rev_id = AL_REG_FIELD_GET( - chip_id, - PBS_UNIT_CHIP_ID_DEV_REV_ID_MASK, - PBS_UNIT_CHIP_ID_DEV_REV_ID_SHIFT); - } else if (chip_id_dev == PBS_UNIT_CHIP_ID_DEV_ID_PEAKROCK) { + if (chip_id_dev == PBS_UNIT_CHIP_ID_DEV_ID_ALPINE_V1) { + rev_id = AL_PCIE_REV_ID_1; + } else if (chip_id_dev == PBS_UNIT_CHIP_ID_DEV_ID_ALPINE_V2) { struct al_pcie_revx_regs __iomem *regs = (struct al_pcie_revx_regs __iomem *)pcie_reg_base; uint32_t dev_id; @@ -469,20 +458,6 @@ al_pcie_ib_hcrd_os_ob_reads_config_defau al_pcie_port_ib_hcrd_os_ob_reads_config(pcie_port, &ib_hcrd_os_ob_reads_config); }; -/** return AL_TRUE is link started (LTSSM enabled) and AL_FALSE otherwise */ -static al_bool -al_pcie_is_link_started(struct al_pcie_port *pcie_port) -{ - struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs; - - uint32_t port_init = al_reg_read32(regs->app.global_ctrl.port_init); - uint8_t ltssm_en = AL_REG_FIELD_GET(port_init, - PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK, - PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_SHIFT); - - return ltssm_en; -} - /** return AL_TRUE if link is up, AL_FALSE otherwise */ static al_bool al_pcie_check_link( @@ -651,18 +626,6 @@ al_pcie_port_gen3_params_config(struct a } static int -al_pcie_port_tl_credits_config( - struct al_pcie_port *pcie_port, - const struct al_pcie_tl_credits_params *tl_credits __attribute__((__unused__))) -{ - al_err("PCIe %d: transport layer credits config not implemented\n", - pcie_port->port_id); - - return -ENOSYS; - -} - -static int al_pcie_port_pf_params_config(struct al_pcie_pf *pcie_pf, const struct al_pcie_pf_config_params *pf_params) { @@ -680,22 +643,21 @@ al_pcie_port_pf_params_config(struct al_ regs->core_space[pf_num].pcie_pm_cap_base, AL_FIELD_MASK(26, 25) | AL_FIELD_MASK(31, 28), 0); - /* Disable FLR capability */ + /* Set/Clear FLR bit */ if (pf_params->cap_flr_dis) al_reg_write32_masked( regs->core_space[pf_num].pcie_dev_cap_base, - AL_BIT(28), 0); + AL_PCI_EXP_DEVCAP_FLR, 0); + else + al_reg_write32_masked( + regs->core_space[pcie_pf->pf_num].pcie_dev_cap_base, + AL_PCI_EXP_DEVCAP_FLR, AL_PCI_EXP_DEVCAP_FLR); /* Disable ASPM capability */ if (pf_params->cap_aspm_dis) { al_reg_write32_masked( regs->core_space[pf_num].pcie_cap_base + (AL_PCI_EXP_LNKCAP >> 2), AL_PCI_EXP_LNKCAP_ASPMS, 0); - } else if (pcie_port->rev_id == AL_PCIE_REV_ID_0) { - al_warn("%s: ASPM support is enabled, please disable it\n", - __func__); - ret = -EINVAL; - goto done; } if (!pf_params->bar_params_valid) { @@ -743,8 +705,9 @@ al_pcie_port_pf_params_config(struct al_ if (params->memory_space) { if (size < AL_PCIE_MIN_MEMORY_BAR_SIZE) { - al_err("PCIe %d: memory BAR %d: size (0x%llx) less that minimal allowed value\n", - pcie_port->port_id, bar_idx, size); + al_err("PCIe %d: memory BAR %d: size (0x%jx) less that minimal allowed value\n", + pcie_port->port_id, bar_idx, + (uintmax_t)size); ret = -EINVAL; goto done; } @@ -756,8 +719,9 @@ al_pcie_port_pf_params_config(struct al_ } if (size < AL_PCIE_MIN_IO_BAR_SIZE) { - al_err("PCIe %d: IO BAR %d: size (0x%llx) less that minimal allowed value\n", - pcie_port->port_id, bar_idx, size); + al_err("PCIe %d: IO BAR %d: size (0x%jx) less that minimal allowed value\n", + pcie_port->port_id, bar_idx, + (uintmax_t)size); ret = -EINVAL; goto done; } @@ -765,9 +729,9 @@ al_pcie_port_pf_params_config(struct al_ /* size must be power of 2 */ if (size & (size - 1)) { - al_err("PCIe %d: BAR %d:size (0x%llx) must be " + al_err("PCIe %d: BAR %d:size (0x%jx) must be " "power of 2\n", - pcie_port->port_id, bar_idx, size); + pcie_port->port_id, bar_idx, (uintmax_t)size); ret = -EINVAL; goto done; } @@ -826,8 +790,7 @@ al_pcie_port_pf_params_config(struct al_ } /* Open CPU generated msi and legacy interrupts in pcie wrapper logic */ - if ((pcie_port->rev_id == AL_PCIE_REV_ID_0) || - (pcie_port->rev_id == AL_PCIE_REV_ID_1)) { + if (pcie_port->rev_id == AL_PCIE_REV_ID_1) { al_reg_write32(regs->app.soc_int[pf_num].mask_inta_leg_0, (1 << 21)); } else if ((pcie_port->rev_id == AL_PCIE_REV_ID_2) || (pcie_port->rev_id == AL_PCIE_REV_ID_3)) { @@ -853,13 +816,7 @@ al_pcie_port_pf_params_config(struct al_ * Restore the original value after the write to app.soc.mask_msi_leg_0 * register. */ - if (pcie_port->rev_id == AL_PCIE_REV_ID_0) { - uint32_t backup; - - backup = al_reg_read32(®s->app.int_grp_a->mask); - al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_0, (1 << 22)); - al_reg_write32(®s->app.int_grp_a->mask, backup); - } else if (pcie_port->rev_id == AL_PCIE_REV_ID_1) { + if (pcie_port->rev_id == AL_PCIE_REV_ID_1) { al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_0, (1 << 22)); } else if ((pcie_port->rev_id == AL_PCIE_REV_ID_2) || (pcie_port->rev_id == AL_PCIE_REV_ID_3)) { @@ -878,22 +835,6 @@ done: return ret; } -static void -al_pcie_port_features_config( - struct al_pcie_port *pcie_port, - const struct al_pcie_features *features) -{ - struct al_pcie_regs *regs = pcie_port->regs; - - al_assert(pcie_port->rev_id > AL_PCIE_REV_ID_0); - - al_reg_write32_masked( - ®s->app.ctrl_gen->features, - PCIE_W_CTRL_GEN_FEATURES_SATA_EP_MSI_FIX, - features->sata_ep_msi_fix ? - PCIE_W_CTRL_GEN_FEATURES_SATA_EP_MSI_FIX : 0); -} - static int al_pcie_port_sris_config( struct al_pcie_port *pcie_port, @@ -916,6 +857,9 @@ al_pcie_port_sris_config( switch (pcie_port->rev_id) { case AL_PCIE_REV_ID_3: + al_reg_write32_masked(®s->app.cfg_func_ext->cfg, + PCIE_W_CFG_FUNC_EXT_CFG_APP_SRIS_MODE, + PCIE_W_CFG_FUNC_EXT_CFG_APP_SRIS_MODE); case AL_PCIE_REV_ID_2: al_reg_write32_masked(regs->app.global_ctrl.sris_kp_counter, PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_SRIS_MASK | @@ -989,6 +933,34 @@ al_pcie_port_max_num_of_pfs_get(struct a return 1; } +/** Enable ecrc generation in outbound atu (Addressing RMN: 5119) */ +static void al_pcie_ecrc_gen_ob_atu_enable(struct al_pcie_port *pcie_port, unsigned int pf_num) +{ + struct al_pcie_regs *regs = pcie_port->regs; + int max_ob_atu = (pcie_port->rev_id == AL_PCIE_REV_ID_3) ? + AL_PCIE_REV_3_ATU_NUM_OUTBOUND_REGIONS : AL_PCIE_REV_1_2_ATU_NUM_OUTBOUND_REGIONS; + int i; + for (i = 0; i < max_ob_atu; i++) { + al_bool enable = 0; + uint32_t reg = 0; + unsigned int func_num; + AL_REG_FIELD_SET(reg, 0xF, 0, i); + AL_REG_BIT_VAL_SET(reg, 31, AL_PCIE_ATU_DIR_OUTBOUND); + al_reg_write32(®s->port_regs->iatu.index, reg); + reg = al_reg_read32(®s->port_regs->iatu.cr2); + enable = AL_REG_BIT_GET(reg, 31) ? AL_TRUE : AL_FALSE; + reg = al_reg_read32(®s->port_regs->iatu.cr1); + func_num = AL_REG_FIELD_GET(reg, + PCIE_IATU_CR1_FUNC_NUM_MASK, + PCIE_IATU_CR1_FUNC_NUM_SHIFT); + if ((enable == AL_TRUE) && (pf_num == func_num)) { + /* Set TD bit */ + AL_REG_BIT_SET(reg, 8); + al_reg_write32(®s->port_regs->iatu.cr1, reg); + } + } +} + /******************************************************************************/ /***************************** API Implementation *****************************/ /******************************************************************************/ @@ -1025,12 +997,13 @@ al_pcie_port_handle_init( /* Zero all regs */ al_memset(pcie_port->regs, 0, sizeof(struct al_pcie_regs)); - if ((pcie_port->rev_id == AL_PCIE_REV_ID_0) || - (pcie_port->rev_id == AL_PCIE_REV_ID_1)) { + if (pcie_port->rev_id == AL_PCIE_REV_ID_1) { struct al_pcie_rev1_regs __iomem *regs = (struct al_pcie_rev1_regs __iomem *)pcie_reg_base; pcie_port->regs->axi.ctrl.global = ®s->axi.ctrl.global; + pcie_port->regs->axi.ctrl.master_rctl = ®s->axi.ctrl.master_rctl; + pcie_port->regs->axi.ctrl.master_ctl = ®s->axi.ctrl.master_ctl; pcie_port->regs->axi.ctrl.master_arctl = ®s->axi.ctrl.master_arctl; pcie_port->regs->axi.ctrl.master_awctl = ®s->axi.ctrl.master_awctl; pcie_port->regs->axi.ctrl.slv_ctl = ®s->axi.ctrl.slv_ctl; @@ -1059,20 +1032,21 @@ al_pcie_port_handle_init( pcie_port->regs->app.global_ctrl.pm_control = ®s->app.global_ctrl.pm_control; pcie_port->regs->app.global_ctrl.events_gen[0] = ®s->app.global_ctrl.events_gen; pcie_port->regs->app.debug = ®s->app.debug; + pcie_port->regs->app.soc_int[0].status_0 = ®s->app.soc_int.status_0; + pcie_port->regs->app.soc_int[0].status_1 = ®s->app.soc_int.status_1; + pcie_port->regs->app.soc_int[0].status_2 = ®s->app.soc_int.status_2; pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = ®s->app.soc_int.mask_inta_leg_0; + pcie_port->regs->app.soc_int[0].mask_inta_leg_1 = ®s->app.soc_int.mask_inta_leg_1; + pcie_port->regs->app.soc_int[0].mask_inta_leg_2 = ®s->app.soc_int.mask_inta_leg_2; pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = ®s->app.soc_int.mask_msi_leg_0; + pcie_port->regs->app.soc_int[0].mask_msi_leg_1 = ®s->app.soc_int.mask_msi_leg_1; + pcie_port->regs->app.soc_int[0].mask_msi_leg_2 = ®s->app.soc_int.mask_msi_leg_2; pcie_port->regs->app.ctrl_gen = ®s->app.ctrl_gen; pcie_port->regs->app.parity = ®s->app.parity; pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair; pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair; - - if (pcie_port->rev_id == AL_PCIE_REV_ID_0) { - pcie_port->regs->app.int_grp_a = ®s->app.int_grp_a_m0; - pcie_port->regs->app.int_grp_b = ®s->app.int_grp_b_m0; - } else { - pcie_port->regs->app.int_grp_a = ®s->app.int_grp_a; - pcie_port->regs->app.int_grp_b = ®s->app.int_grp_b; - } + pcie_port->regs->app.int_grp_a = ®s->app.int_grp_a; + pcie_port->regs->app.int_grp_b = ®s->app.int_grp_b; pcie_port->regs->core_space[0].config_header = regs->core_space.config_header; pcie_port->regs->core_space[0].pcie_pm_cap_base = ®s->core_space.pcie_pm_cap_base; @@ -1091,6 +1065,8 @@ al_pcie_port_handle_init( (struct al_pcie_rev2_regs __iomem *)pcie_reg_base; pcie_port->regs->axi.ctrl.global = ®s->axi.ctrl.global; + pcie_port->regs->axi.ctrl.master_rctl = ®s->axi.ctrl.master_rctl; + pcie_port->regs->axi.ctrl.master_ctl = ®s->axi.ctrl.master_ctl; pcie_port->regs->axi.ctrl.master_arctl = ®s->axi.ctrl.master_arctl; pcie_port->regs->axi.ctrl.master_awctl = ®s->axi.ctrl.master_awctl; pcie_port->regs->axi.ctrl.slv_ctl = ®s->axi.ctrl.slv_ctl; @@ -1100,6 +1076,10 @@ al_pcie_port_handle_init( pcie_port->regs->axi.ob_ctrl.io_start_h = ®s->axi.ob_ctrl.io_start_h; pcie_port->regs->axi.ob_ctrl.io_limit_l = ®s->axi.ob_ctrl.io_limit_l; pcie_port->regs->axi.ob_ctrl.io_limit_h = ®s->axi.ob_ctrl.io_limit_h; + pcie_port->regs->axi.ob_ctrl.tgtid_reg_ovrd = ®s->axi.ob_ctrl.tgtid_reg_ovrd; + pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_sel = ®s->axi.ob_ctrl.addr_high_reg_ovrd_sel; + pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_value = ®s->axi.ob_ctrl.addr_high_reg_ovrd_value; + pcie_port->regs->axi.ob_ctrl.addr_size_replace = ®s->axi.ob_ctrl.addr_size_replace; pcie_port->regs->axi.pcie_global.conf = ®s->axi.pcie_global.conf; pcie_port->regs->axi.conf.zero_lane0 = ®s->axi.conf.zero_lane0; pcie_port->regs->axi.conf.zero_lane1 = ®s->axi.conf.zero_lane1; @@ -1120,11 +1100,20 @@ al_pcie_port_handle_init( pcie_port->regs->app.global_ctrl.events_gen[0] = ®s->app.global_ctrl.events_gen; pcie_port->regs->app.global_ctrl.corr_err_sts_int = ®s->app.global_ctrl.pended_corr_err_sts_int; pcie_port->regs->app.global_ctrl.uncorr_err_sts_int = ®s->app.global_ctrl.pended_uncorr_err_sts_int; + pcie_port->regs->app.global_ctrl.sris_kp_counter = ®s->app.global_ctrl.sris_kp_counter_value; pcie_port->regs->app.debug = ®s->app.debug; pcie_port->regs->app.ap_user_send_msg = ®s->app.ap_user_send_msg; + pcie_port->regs->app.soc_int[0].status_0 = ®s->app.soc_int.status_0; + pcie_port->regs->app.soc_int[0].status_1 = ®s->app.soc_int.status_1; + pcie_port->regs->app.soc_int[0].status_2 = ®s->app.soc_int.status_2; + pcie_port->regs->app.soc_int[0].status_3 = ®s->app.soc_int.status_3; pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = ®s->app.soc_int.mask_inta_leg_0; + pcie_port->regs->app.soc_int[0].mask_inta_leg_1 = ®s->app.soc_int.mask_inta_leg_1; + pcie_port->regs->app.soc_int[0].mask_inta_leg_2 = ®s->app.soc_int.mask_inta_leg_2; pcie_port->regs->app.soc_int[0].mask_inta_leg_3 = ®s->app.soc_int.mask_inta_leg_3; pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = ®s->app.soc_int.mask_msi_leg_0; + pcie_port->regs->app.soc_int[0].mask_msi_leg_1 = ®s->app.soc_int.mask_msi_leg_1; + pcie_port->regs->app.soc_int[0].mask_msi_leg_2 = ®s->app.soc_int.mask_msi_leg_2; pcie_port->regs->app.soc_int[0].mask_msi_leg_3 = ®s->app.soc_int.mask_msi_leg_3; pcie_port->regs->app.ctrl_gen = ®s->app.ctrl_gen; pcie_port->regs->app.parity = ®s->app.parity; @@ -1150,6 +1139,8 @@ al_pcie_port_handle_init( struct al_pcie_rev3_regs __iomem *regs = (struct al_pcie_rev3_regs __iomem *)pcie_reg_base; pcie_port->regs->axi.ctrl.global = ®s->axi.ctrl.global; + pcie_port->regs->axi.ctrl.master_rctl = ®s->axi.ctrl.master_rctl; + pcie_port->regs->axi.ctrl.master_ctl = ®s->axi.ctrl.master_ctl; pcie_port->regs->axi.ctrl.master_arctl = ®s->axi.ctrl.master_arctl; pcie_port->regs->axi.ctrl.master_awctl = ®s->axi.ctrl.master_awctl; pcie_port->regs->axi.ctrl.slv_ctl = ®s->axi.ctrl.slv_ctl; @@ -1159,6 +1150,13 @@ al_pcie_port_handle_init( pcie_port->regs->axi.ob_ctrl.io_start_h = ®s->axi.ob_ctrl.io_start_h; pcie_port->regs->axi.ob_ctrl.io_limit_l = ®s->axi.ob_ctrl.io_limit_l; pcie_port->regs->axi.ob_ctrl.io_limit_h = ®s->axi.ob_ctrl.io_limit_h; + pcie_port->regs->axi.ob_ctrl.io_addr_mask_h = ®s->axi.ob_ctrl.io_addr_mask_h; + pcie_port->regs->axi.ob_ctrl.ar_msg_addr_mask_h = ®s->axi.ob_ctrl.ar_msg_addr_mask_h; + pcie_port->regs->axi.ob_ctrl.aw_msg_addr_mask_h = ®s->axi.ob_ctrl.aw_msg_addr_mask_h; + pcie_port->regs->axi.ob_ctrl.tgtid_reg_ovrd = ®s->axi.ob_ctrl.tgtid_reg_ovrd; + pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_sel = ®s->axi.ob_ctrl.addr_high_reg_ovrd_sel; + pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_value = ®s->axi.ob_ctrl.addr_high_reg_ovrd_value; + pcie_port->regs->axi.ob_ctrl.addr_size_replace = ®s->axi.ob_ctrl.addr_size_replace; pcie_port->regs->axi.pcie_global.conf = ®s->axi.pcie_global.conf; pcie_port->regs->axi.conf.zero_lane0 = ®s->axi.conf.zero_lane0; pcie_port->regs->axi.conf.zero_lane1 = ®s->axi.conf.zero_lane1; @@ -1213,9 +1211,17 @@ al_pcie_port_handle_init( pcie_port->regs->app.debug = ®s->app.debug; for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) { + pcie_port->regs->app.soc_int[i].status_0 = ®s->app.soc_int_per_func[i].status_0; + pcie_port->regs->app.soc_int[i].status_1 = ®s->app.soc_int_per_func[i].status_1; + pcie_port->regs->app.soc_int[i].status_2 = ®s->app.soc_int_per_func[i].status_2; + pcie_port->regs->app.soc_int[i].status_3 = ®s->app.soc_int_per_func[i].status_3; pcie_port->regs->app.soc_int[i].mask_inta_leg_0 = ®s->app.soc_int_per_func[i].mask_inta_leg_0; + pcie_port->regs->app.soc_int[i].mask_inta_leg_1 = ®s->app.soc_int_per_func[i].mask_inta_leg_1; + pcie_port->regs->app.soc_int[i].mask_inta_leg_2 = ®s->app.soc_int_per_func[i].mask_inta_leg_2; pcie_port->regs->app.soc_int[i].mask_inta_leg_3 = ®s->app.soc_int_per_func[i].mask_inta_leg_3; pcie_port->regs->app.soc_int[i].mask_msi_leg_0 = ®s->app.soc_int_per_func[i].mask_msi_leg_0; + pcie_port->regs->app.soc_int[i].mask_msi_leg_1 = ®s->app.soc_int_per_func[i].mask_msi_leg_1; + pcie_port->regs->app.soc_int[i].mask_msi_leg_2 = ®s->app.soc_int_per_func[i].mask_msi_leg_2; pcie_port->regs->app.soc_int[i].mask_msi_leg_3 = ®s->app.soc_int_per_func[i].mask_msi_leg_3; } @@ -1224,6 +1230,7 @@ al_pcie_port_handle_init( pcie_port->regs->app.parity = ®s->app.parity; pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair; pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair; + pcie_port->regs->app.cfg_func_ext = ®s->app.cfg_func_ext; for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) pcie_port->regs->app.status_per_func[i] = ®s->app.status_per_func[i]; @@ -1260,6 +1267,10 @@ al_pcie_port_handle_init( /* set maximum number of physical functions */ pcie_port->max_num_of_pfs = al_pcie_port_max_num_of_pfs_get(pcie_port); + /* Clear 'nof_p_hdr' & 'nof_np_hdr' to later know if they where changed by the user */ + pcie_port->ib_hcrd_config.nof_np_hdr = 0; + pcie_port->ib_hcrd_config.nof_p_hdr = 0; + al_dbg("pcie port handle initialized. port id: %d, rev_id %d, regs base %p\n", port_id, pcie_port->rev_id, pcie_reg_base); return 0; @@ -1294,6 +1305,12 @@ al_pcie_pf_handle_init( return 0; } +/** Get port revision ID */ +int al_pcie_port_rev_id_get(struct al_pcie_port *pcie_port) +{ + return pcie_port->rev_id; +} + /************************** Pre PCIe Port Enable API **************************/ /** configure pcie operating mode (root complex or endpoint) */ @@ -1346,7 +1363,7 @@ al_pcie_port_operating_mode_config( "EndPoint" : "Root Complex"); return 0; } - al_info("PCIe %d: set operating mode to %s\n", + al_dbg("PCIe %d: set operating mode to %s\n", pcie_port->port_id, (mode == AL_PCIE_OPERATING_MODE_EP) ? "EndPoint" : "Root Complex"); AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK, @@ -1362,6 +1379,7 @@ int al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes) { struct al_pcie_regs *regs = pcie_port->regs; + uint32_t active_lanes_val; if (al_pcie_port_is_enabled(pcie_port)) { al_err("PCIe %d: already enabled, cannot set max lanes\n", @@ -1370,7 +1388,7 @@ al_pcie_port_max_lanes_set(struct al_pci } /* convert to bitmask format (4 ->'b1111, 2 ->'b11, 1 -> 'b1) */ - uint32_t active_lanes_val = AL_PCIE_PARSE_LANES(lanes); + active_lanes_val = AL_PCIE_PARSE_LANES(lanes); al_reg_write32_masked(regs->axi.pcie_global.conf, (pcie_port->rev_id == AL_PCIE_REV_ID_3) ? @@ -1387,11 +1405,7 @@ al_pcie_port_max_num_of_pfs_set( struct al_pcie_port *pcie_port, uint8_t max_num_of_pfs) { - if (al_pcie_port_is_enabled(pcie_port)) { - al_err("PCIe %d: already enabled, cannot set max num of PFs\n", - pcie_port->port_id); - return -EINVAL; - } + struct al_pcie_regs *regs = pcie_port->regs; if (pcie_port->rev_id == AL_PCIE_REV_ID_3) al_assert(max_num_of_pfs <= REV3_MAX_NUM_OF_PFS); @@ -1400,6 +1414,33 @@ al_pcie_port_max_num_of_pfs_set( pcie_port->max_num_of_pfs = max_num_of_pfs; + if (al_pcie_port_is_enabled(pcie_port) && (pcie_port->rev_id == AL_PCIE_REV_ID_3)) { + enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port); + + al_bool is_multi_pf = + ((op_mode == AL_PCIE_OPERATING_MODE_EP) && (pcie_port->max_num_of_pfs > 1)); + + /* Set maximum physical function numbers */ + al_reg_write32_masked( + ®s->port_regs->timer_ctrl_max_func_num, + PCIE_PORT_GEN3_MAX_FUNC_NUM, + pcie_port->max_num_of_pfs - 1); + + al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE); + + /** + * in EP mode, when we have more than 1 PF we need to assert + * multi-pf support so the host scan all PFs + */ + al_reg_write32_masked((uint32_t __iomem *) + (®s->core_space[0].config_header[0] + + (PCIE_BIST_HEADER_TYPE_BASE >> 2)), + PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK, + is_multi_pf ? PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK : 0); + + al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE); + } + return 0; } @@ -1503,6 +1544,28 @@ al_pcie_operating_mode_get( return AL_PCIE_OPERATING_MODE_UNKNOWN; } +/* PCIe AXI quality of service configuration */ +void al_pcie_axi_qos_config( + struct al_pcie_port *pcie_port, + unsigned int arqos, + unsigned int awqos) +{ + struct al_pcie_regs *regs = pcie_port->regs; + + al_assert(pcie_port); + al_assert(arqos <= PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_VAL_MAX); + al_assert(awqos <= PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_VAL_MAX); + + al_reg_write32_masked( + regs->axi.ctrl.master_arctl, + PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_MASK, + arqos << PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_SHIFT); + al_reg_write32_masked( + regs->axi.ctrl.master_awctl, + PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_MASK, + awqos << PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_SHIFT); +} + /**************************** PCIe Port Enable API ****************************/ /** Enable PCIe port (deassert reset) */ @@ -1518,17 +1581,19 @@ al_pcie_port_enable(struct al_pcie_port /** * Set inbound header credit and outstanding outbound reads defaults + * if the port initiator doesn't set it. * Must be called before port enable (PCIE_EXIST) */ - al_pcie_ib_hcrd_os_ob_reads_config_default(pcie_port); + if ((pcie_port->ib_hcrd_config.nof_np_hdr == 0) || + (pcie_port->ib_hcrd_config.nof_p_hdr == 0)) + al_pcie_ib_hcrd_os_ob_reads_config_default(pcie_port); /* * Disable ATS capability * - must be done before core reset deasserted * - rev_id 0 - no effect, but no harm */ - if ((pcie_port->rev_id == AL_PCIE_REV_ID_0) || - (pcie_port->rev_id == AL_PCIE_REV_ID_1) || *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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