From owner-freebsd-acpi@FreeBSD.ORG Wed Apr 28 14:18:27 2004 Return-Path: Delivered-To: freebsd-acpi@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 8CCCB16A4CE for ; Wed, 28 Apr 2004 14:18:27 -0700 (PDT) Received: from postal1.es.net (postal1.es.net [198.128.3.205]) by mx1.FreeBSD.org (Postfix) with ESMTP id 7D90B43D1F for ; Wed, 28 Apr 2004 14:18:27 -0700 (PDT) (envelope-from oberman@es.net) Received: from ptavv.es.net ([198.128.4.29]) by postal1.es.net (Postal Node 1) with ESMTP (SSL) id IBA74465; Wed, 28 Apr 2004 14:18:26 -0700 Received: from ptavv (localhost [127.0.0.1]) by ptavv.es.net (Tachyon Server) with ESMTP id A02195D07; Wed, 28 Apr 2004 14:18:26 -0700 (PDT) To: Nate Lawson In-reply-to: Your message of "Wed, 28 Apr 2004 13:15:13 PDT." <20040428131247.K88558@root.org> Date: Wed, 28 Apr 2004 14:18:26 -0700 From: "Kevin Oberman" Message-Id: <20040428211826.A02195D07@ptavv.es.net> cc: freebsd-acpi@freebsd.org cc: Jeffrey Katcher Subject: Re: Fan Control Success on IBM T40? (another quick Q) X-BeenThere: freebsd-acpi@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: ACPI and power management development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Apr 2004 21:18:27 -0000 > Date: Wed, 28 Apr 2004 13:15:13 -0700 (PDT) > From: Nate Lawson > Sender: owner-freebsd-acpi@freebsd.org > > I forgot to add -- the reason the clock rate announced at boot time is > different is because the test for CPU TSC is done before acpi is enabled. > At some point when the SMI is disabled and acpi enabled, the clock rate is > switched by your BIOS to the lower rate. You can see this because the > clock rate announced by the TSC timecounter will be ~600 mhz while the > initial boot clock rate will list ~1600 mhz. This all makes sense, but it conflicts a bit with my observations. (Probably implies something bad about my powers of observation.) I boot and the system (T30) is running at 1.8 GHz. I throttle the CPU. Testing clearly shows that the throttling is working. I use the test you suggested of calculating an MD5 hash of a big string of zeros. But, when I "count cycles" to test the CPU speed (code appended), I still see 1.8 GHz. Why don't I see the speed reduced when throttling? I suspect my lack of fundamental understanding of the interactions of throttling and the ACPI clock. -- R. Kevin Oberman, Network Engineer Energy Sciences Network (ESnet) Ernest O. Lawrence Berkeley National Laboratory (Berkeley Lab) E-mail: oberman@es.net Phone: +1 510 486-8634 /* * $Id: MHz.c,v 1.4 2001/05/21 18:58:01 davej Exp $ * This file is part of x86info. * (C) 2001 Dave Jones. * * Licensed under the terms of the GNU GPL License version 2. * * Estimate CPU MHz routine by Andrea Arcangeli * Small changes by David Sterba * */ #include #include #include #include __inline__ unsigned long long int rdtsc() { unsigned long long int x; __asm__ volatile (".byte 0x0f, 0x31" : "=A" (x)); return x; } char *estimate_MHz() { char *buffer; struct timezone tz; struct timeval tvstart, tvstop; unsigned long long int cycles[2]; /* gotta be 64 bit */ unsigned int microseconds; /* total time taken */ memset(&tz, 0, sizeof(tz)); /* get this function in cached memory */ gettimeofday(&tvstart, &tz); cycles[0] = rdtsc(); gettimeofday(&tvstart, &tz); /* we don't trust that this is any specific length of time */ usleep(100); cycles[1] = rdtsc(); gettimeofday(&tvstop, &tz); microseconds = ((tvstop.tv_sec-tvstart.tv_sec)*1000000) + (tvstop.tv_usec-tvstart.tv_usec); buffer = malloc(sizeof(char)*512); sprintf(buffer, "%lldMHz", (cycles[1]-cycles[0])/microseconds); return buffer; }