From owner-freebsd-sparc64@FreeBSD.ORG Fri Aug 29 14:16:42 2003 Return-Path: Delivered-To: freebsd-sparc64@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id E210C16A4BF for ; Fri, 29 Aug 2003 14:16:42 -0700 (PDT) Received: from ns1.xcllnt.net (209-128-86-226.BAYAREA.NET [209.128.86.226]) by mx1.FreeBSD.org (Postfix) with ESMTP id 753FD43FAF for ; Fri, 29 Aug 2003 14:16:41 -0700 (PDT) (envelope-from marcel@xcllnt.net) Received: from athlon.pn.xcllnt.net (athlon.pn.xcllnt.net [192.168.4.3]) by ns1.xcllnt.net (8.12.9/8.12.9) with ESMTP id h7TLGfwO001273 for ; Fri, 29 Aug 2003 14:16:41 -0700 (PDT) (envelope-from marcel@piii.pn.xcllnt.net) Received: from athlon.pn.xcllnt.net (localhost [127.0.0.1]) by athlon.pn.xcllnt.net (8.12.9/8.12.9) with ESMTP id h7TLGfhs000665 for ; Fri, 29 Aug 2003 14:16:41 -0700 (PDT) (envelope-from marcel@athlon.pn.xcllnt.net) Received: (from marcel@localhost) by athlon.pn.xcllnt.net (8.12.9/8.12.9/Submit) id h7TLGfhl000664 for sparc64@FreeBSD.org; Fri, 29 Aug 2003 14:16:41 -0700 (PDT) (envelope-from marcel) Date: Fri, 29 Aug 2003 14:16:41 -0700 From: Marcel Moolenaar To: sparc64@FreeBSD.org Message-ID: <20030829211641.GA628@athlon.pn.xcllnt.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.4i Subject: Q: resource range for SBus oddity X-BeenThere: freebsd-sparc64@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Porting FreeBSD to the Sparc List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Aug 2003 21:16:43 -0000 Gang, I'm playing with uart(4) on Jake's u2, which has 2 zs(4) devices attached to sbus. A GENERIC kernel gives me the following: : zs0: mem 0x1100000-0x1100003 irq 2024 on sbus0 zstty0: on zs0 zstty0: console 9600,8,n,1,- zstty1: on zs0 sbus0: , type serial (no driver attached) : A kernel with uart(4) yields currently (it's a WIP): : puc0: mem 0x1100000-0x1100003 irq 2024 on sbus0 uart0: on puc0 uart0: console uart1: on puc0 puc1: mem 0x1000000-0x1000003 irq 2024 on sbus0 uart2: on puc1 uart3: on puc1 : As you can see, the memory I/O resource is 4 bytes wide. However, the channel A registers on the z8530 chip are at offsets 4 (control) and 6 (data). This lies outside the reserved range. I would think that with 2 channels and 2 addressable registers per channel we would be using offsets 0-3. Question: Is there an implied multiplication or division factor? -- Marcel Moolenaar USPA: A-39004 marcel@xcllnt.net