Date: Wed, 16 Oct 1996 01:03:57 -0700 From: Chris Browning <cbrown@aracnet.com> To: smp@freebsd.org Subject: Re: dual-cpu PPRO motherboards... Message-ID: <326496ED.281@aracnet.com> References: <199610150627.OAA18081@spinner.DIALix.COM>
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Peter Wemm wrote: > According to the mpspec, there is a pci->isa mapping system that is > supposed to "sense" when the system switches into symmetric mode and > disable itself when the io apics are activated. So, it depends on how the > ide irq's originate I guess. If they originate as "pci interrupts" that > go through the redirection matrix, then in theory the isa irq14/15 signals > should be freed up. However, Intel could well have hardwired it so that > the piix3 chipset generates isa edge triggered interrupts only and cannot > do pci-style level sensative irq's. Hmm, I'm not sure how the PIIX3 works, since I have never used a machine with one :-). As far as the mapping switching when APIC mode happens, I'm not sure that this happens automatically. The OS may have to move these where it likes. > Is the 8259-workalike in the piix3 in the 430HX chipset or in the other > "big" chip? If the ide and 8259's are on the same chunk of silicon, they > may be hardwired on the chip with the on-chip IDE only being "on" or "off" > on the hardwired configuration. I think the PIIX3 is a standlone chip. Again, I am not too familiar with it, but I think the IDE is built into it. That would probably also include 8259 compatible logic. > > > But what does change is that you have the additional IO APIC INTS 16 thru > > > 23, 4 of which will be available for your PCI cards. Which means they won't > > > have to compete with ISA cards for the 1st 16 INTS. > > > > Wrong. According to the same page I quoted above, interrupts 16-31 are > > reserved for processor > > use. This may be different on a non PPro system. 32-255 are available > > for general purpose use. > > Now, from an OS prespective, you may never see 16-31 and the rest may > > get shifted down, since this > > is all done in HW. > > You are confusing the isa hardware interrupts with the processor's IDT > (interrupt descriptor table). Currently, the 16 isa interrupts are mapped > into IDT entries 32 through 47. With the work Steve's been doing, the IO > Apic's have vector numbers 32 through 55 programmed into them. So, when > the 8259 pics are disabled, the IO APIC produces the exact same interrupt > vectors, just more of them. I don't think that I am confusing these two. I understand what the IDT is. What I am saying is that the APIC bus supports 255 interrupt sources. In your system it seems that you only have one IO APIC (PIIX3) that is limited to 24 interrupts. Now, you could hook up more IO APICs and get more interrupts on the APIC bus, up to 255. For example, my system has 2 IO APICs on the APIC bus, so I can have many more than 24 interrupts on the APIC bus. Of course, most things don't take advantage of this :-(. > Currently the IRQ's are directly mapped in a 1:1 ratio to the IDT table, > but there's no need to. If there's a space squeeze to fit all the devices > into a 32 bit mask, for example, there's nothing stopping us compacting it. > > Only one IO apic is supported at present, but I think we know about one > motherboard that has two IO apic's already (and two pci busses, etc), so > we've got to deal with having 48 or so hardware IRQ's on currently > existing hardware. Yeap, I am looking at one right now :-) > The present irq masking architecture depends on being > able to locate the originating IO apic quickly to mask further interrupts > during the handler, so having both IO apics generating overlapping IDT > vectors is "too hard" at present. I'm sure Steve will yell if I've > misunderstood his code. > > > You will have to compete for the ISA interrupts still, unless you have a > > lot of PCI devices > > you don't want to be visible at boot time (i.e. moving your super-fancy > > SCSI card to an > > interrupt above 15 will mean you can't see it until you get into the OS) > > No, this is not an issue.. The BIOS boots in "virtual wire" mode, with > the PCI->ISA mapping active. Not all BIOSes boot in VWM. > So, an arbitrary PCI interrupt may already > be hardwired to the IO APIC on int18, and _also_ be switched through to > the inputs of the 8259-clone PICs. The APIC only sees the given pci IRQ > line on interrupt 18, and never sees the result of the pci->isa mapping to > the 8259 pics.
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