Date: Fri, 27 Jun 1997 11:40:22 +0200 From: Stefan Esser <se@FreeBSD.ORG> To: dg@root.com Cc: Jon Inouye <jinouye@cse.ogi.edu>, "Jordan K. Hubbard" <jkh@time.cdrom.com>, freebsd-hardware@FreeBSD.ORG Subject: Re: IRQ assignment for PII motherboards Message-ID: <19970627114022.32725@mi.uni-koeln.de> In-Reply-To: <199706270107.SAA10980@implode.root.com>; from David Greenman on Thu, Jun 26, 1997 at 06:07:09PM -0700 References: <Pine.HPP.3.95.970626170217.4996F-100000@indurain.cse.ogi.edu> <199706270107.SAA10980@implode.root.com>
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On Jun 26, David Greenman <dg@root.com> wrote: > I was able to get the Pro/100B, in a system with a pair of ahc3940's, to > get assigned to a non-shared interrupt by playing around with which slots > the cards were plugged into. It took about 3 tries to find the right order > (including leaving a slot empty), but I finally found an arrangement that > worked. My understanding is that the shared irq assignment isn't a function > of the BIOS, but rather a function of the slot the card is in and how it > is wired compared to the others. The motherboard I did this in wasn't made > by Intel, but the same principles should still apply. Interrupts should not be shared, unless at least one PCI card in the system either: 1) contains a PCI to PCI bridge, or 2) contains a multi-function PCI chip. The PCI spec requires all other cards to only use PCI IntA, if an interrupt line is required at all, and I know of no current 4 slot PCI motherboard, that can't assign a unique IRQ to the PCI IntA pin of each slot. As has been discussed before, the IntA pin of each slot is wired to IntB of its one neighbor, and IntD of the other one. (Or, perhaps easier to understand: IntB of the slot is wired to IntA of its one neighbor and IntC of its other neighbor.) This is repeated for all slots, and thus a safe way to force use of shared interrupts is to place any PCI card between two AH3940 cards :) Int A B C D Slot 1 o o o o- to IntA of slot 4 / / / / Slot 2 o o o o- to IntA of slot 1 / / / / Slot 3 o o o o- to IntA of slot 2 / / / / Slot 4 o o o o- to IntA of slot 3 / (from IntD of Slot 4) As also has been discussed before, there are no INTR_FAST support in the current PCI code (the flag has just not been passed down to the low level code, and nobody ever bothered to make PCI interrupt handlers conform to the very strict requirements of a fast interrupt handler ...). This means, that PCI interrupts may introduce higher latencies than highly optimized interrupt handlers for some ISA devices. This can be fixed (and the PCI interrupt registration code in -current allows to specify the INTR_FAST flag), but there will be some additional work required to make this work for the shared+fast case ... Regards, STefan
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