From owner-svn-src-head@FreeBSD.ORG Fri Jul 30 12:45:01 2010 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 0FCF3106566B; Fri, 30 Jul 2010 12:45:01 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id F07EF8FC13; Fri, 30 Jul 2010 12:45:00 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o6UCj0km063991; Fri, 30 Jul 2010 12:45:00 GMT (envelope-from jchandra@svn.freebsd.org) Received: (from jchandra@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o6UCj0u2063986; Fri, 30 Jul 2010 12:45:00 GMT (envelope-from jchandra@svn.freebsd.org) Message-Id: <201007301245.o6UCj0u2063986@svn.freebsd.org> From: "Jayachandran C." Date: Fri, 30 Jul 2010 12:45:00 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r210644 - head/sys/mips/mips X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Jul 2010 12:45:01 -0000 Author: jchandra Date: Fri Jul 30 12:45:00 2010 New Revision: 210644 URL: http://svn.freebsd.org/changeset/base/210644 Log: n64 support - enable UX bit in STATUS for kernel and userspace. - enable UX in kernel start, and kernel entry - keep UX flag in cpu_fork and cpu_set_upcall - enable UX for userspace Modified: head/sys/mips/mips/exception.S head/sys/mips/mips/locore.S head/sys/mips/mips/pm_machdep.c head/sys/mips/mips/vm_machdep.c Modified: head/sys/mips/mips/exception.S ============================================================================== --- head/sys/mips/mips/exception.S Fri Jul 30 12:36:40 2010 (r210643) +++ head/sys/mips/mips/exception.S Fri Jul 30 12:45:00 2010 (r210644) @@ -238,7 +238,7 @@ SlowFault: #elif defined(TARGET_XLR_XLS) #define CLEAR_STATUS \ mfc0 a0, MIPS_COP_0_STATUS ;\ - li a2, (MIPS_SR_KX | MIPS_SR_COP_2_BIT) ; \ + li a2, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT) ; \ or a0, a0, a2 ; \ li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER) ; \ and a0, a0, a2 ; \ @@ -484,7 +484,7 @@ NNON_LEAF(MipsUserGenException, CALLFRAM #if defined(CPU_CNMIPS) or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX) #elif defined(TARGET_XLR_XLS) - or t0, t0, (MIPS_SR_KX | MIPS_SR_COP_2_BIT) + or t0, t0, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT) #endif mtc0 t0, MIPS_COP_0_STATUS PTR_ADDU a0, k1, U_PCB_REGS @@ -708,7 +708,7 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, r #ifdef CPU_CNMIPS or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX) #elif defined(TARGET_XLR_XLS) - or t0, t0, (MIPS_SR_KX | MIPS_SR_COP_2_BIT) + or t0, t0, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT) #endif mtc0 t0, MIPS_COP_0_STATUS ITLBNOPFIX Modified: head/sys/mips/mips/locore.S ============================================================================== --- head/sys/mips/mips/locore.S Fri Jul 30 12:36:40 2010 (r210643) +++ head/sys/mips/mips/locore.S Fri Jul 30 12:45:00 2010 (r210644) @@ -101,7 +101,7 @@ VECTOR(_locore, unknown) li t0, ~(MIPS_SR_DE | MIPS_SR_SOFT_RESET | MIPS_SR_ERL | MIPS_SR_EXL | MIPS_SR_INT_IE) #elif defined (TARGET_XLR_XLS) /* Set these bits */ - li t1, (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS_SR_KX) + li t1, (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS_SR_KX | MIPS_SR_UX) /* Reset these bits */ li t0, ~(MIPS_SR_BEV | MIPS_SR_SOFT_RESET | MIPS_SR_INT_IE) Modified: head/sys/mips/mips/pm_machdep.c ============================================================================== --- head/sys/mips/mips/pm_machdep.c Fri Jul 30 12:36:40 2010 (r210643) +++ head/sys/mips/mips/pm_machdep.c Fri Jul 30 12:45:00 2010 (r210644) @@ -514,8 +514,10 @@ exec_setregs(struct thread *td, struct i td->td_frame->t9 = imgp->entry_addr & ~3; /* abicall req */ td->td_frame->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | MIPS_SR_INT_IE | (mips_rd_status() & MIPS_SR_INT_MASK); -#if defined(__mips_n32) || defined(__mips_n64) +#if defined(__mips_n32) td->td_frame->sr |= MIPS_SR_PX; +#elif defined(__mips_n64) + td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX; #endif #ifdef CPU_CNMIPS td->td_frame->sr |= MIPS_SR_COP_2_BIT | MIPS_SR_PX | MIPS_SR_UX | Modified: head/sys/mips/mips/vm_machdep.c ============================================================================== --- head/sys/mips/mips/vm_machdep.c Fri Jul 30 12:36:40 2010 (r210643) +++ head/sys/mips/mips/vm_machdep.c Fri Jul 30 12:45:00 2010 (r210644) @@ -148,8 +148,8 @@ cpu_fork(register struct thread *td1,reg pcb2->pcb_context[PCB_REG_S0] = (register_t)(intptr_t)fork_return; pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td2; pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td2->td_frame; - pcb2->pcb_context[PCB_REG_SR] = (MIPS_SR_KX | MIPS_SR_INT_MASK) & - mips_rd_status(); + pcb2->pcb_context[PCB_REG_SR] = mips_rd_status() & + (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_INT_MASK); /* * FREEBSD_DEVELOPERS_FIXME: * Setup any other CPU-Specific registers (Not MIPS Standard) @@ -351,8 +351,8 @@ cpu_set_upcall(struct thread *td, struct pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td; pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td->td_frame; /* Dont set IE bit in SR. sched lock release will take care of it */ - pcb2->pcb_context[PCB_REG_SR] = (MIPS_SR_KX | MIPS_SR_INT_MASK) & - mips_rd_status(); + pcb2->pcb_context[PCB_REG_SR] = mips_rd_status() & + (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_INT_MASK); #ifdef CPU_CNMIPS pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | @@ -414,8 +414,13 @@ cpu_set_upcall_kse(struct thread *td, vo /* * Keep interrupt mask */ - tf->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | (MIPS_SR_INT_MASK & mips_rd_status()) | - MIPS_SR_INT_IE; + td->td_frame->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | MIPS_SR_INT_IE | + (mips_rd_status() & MIPS_SR_INT_MASK); +#if defined(__mips_n32) + td->td_frame->sr |= MIPS_SR_PX; +#elif defined(__mips_n64) + td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX; +#endif #ifdef CPU_CNMIPS tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX;