From owner-freebsd-current@FreeBSD.ORG Wed Jan 11 15:54:57 2012 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id ACE05106564A for ; Wed, 11 Jan 2012 15:54:57 +0000 (UTC) (envelope-from scottl@samsco.org) Received: from pooker.samsco.org (pooker.samsco.org [168.103.85.57]) by mx1.freebsd.org (Postfix) with ESMTP id 7D3188FC1B for ; Wed, 11 Jan 2012 15:54:57 +0000 (UTC) Received: from [127.0.0.1] (pooker.samsco.org [168.103.85.57]) (authenticated bits=0) by pooker.samsco.org (8.14.5/8.14.5) with ESMTP id q0BFsq8p011748; Wed, 11 Jan 2012 08:54:52 -0700 (MST) (envelope-from scottl@samsco.org) Mime-Version: 1.0 (Apple Message framework v1251.1) Content-Type: text/plain; charset=us-ascii From: Scott Long In-Reply-To: <20120110213719.GA92799@onelab2.iet.unipi.it> Date: Wed, 11 Jan 2012 08:54:52 -0700 Content-Transfer-Encoding: quoted-printable Message-Id: References: <20120110213719.GA92799@onelab2.iet.unipi.it> To: Luigi Rizzo X-Mailer: Apple Mail (2.1251.1) X-Spam-Status: No, score=-50.0 required=3.8 tests=ALL_TRUSTED, T_RP_MATCHES_RCVD autolearn=unavailable version=3.3.0 X-Spam-Checker-Version: SpamAssassin 3.3.0 (2010-01-18) on pooker.samsco.org Cc: FreeBSD current Subject: Re: memory barriers in bus_dmamap_sync() ? X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2012 15:54:57 -0000 On Jan 10, 2012, at 2:37 PM, Luigi Rizzo wrote: > I was glancing through manpages and implementations of bus_dma(9) > and i am a bit unclear on what this API (in particular, = bus_dmamap_sync() ) > does in terms of memory barriers. >=20 > I see that the x86/amd64 and ia64 code only does the bounce buffers. > The mips seems to do some coherency-related calls. >=20 > How do we guarantee, say, that a recently built packet is > to memory before issuing the tx command to the NIC ? >=20 In short, i386 and amd64 architectures do bus snooping between the cpu = cache and the memory and bus controllers, and coherency is implicit and = guaranteed. No explicit barriers or flushes are needed for device = mastered DMA. Other CPU architectures have appropriate cache flushes = and memory barriers built into their busdma implementations. Note that = this is a different scenario than device register accesses, which is = essentially host mastered DMA. Scott