Date: Wed, 11 Jan 2012 08:54:52 -0700 From: Scott Long <scottl@samsco.org> To: Luigi Rizzo <rizzo@iet.unipi.it> Cc: FreeBSD current <freebsd-current@freebsd.org> Subject: Re: memory barriers in bus_dmamap_sync() ? Message-ID: <F04F3B40-3CA6-42C4-8654-6787758E2B7E@samsco.org> In-Reply-To: <20120110213719.GA92799@onelab2.iet.unipi.it> References: <20120110213719.GA92799@onelab2.iet.unipi.it>
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On Jan 10, 2012, at 2:37 PM, Luigi Rizzo wrote: > I was glancing through manpages and implementations of bus_dma(9) > and i am a bit unclear on what this API (in particular, = bus_dmamap_sync() ) > does in terms of memory barriers. >=20 > I see that the x86/amd64 and ia64 code only does the bounce buffers. > The mips seems to do some coherency-related calls. >=20 > How do we guarantee, say, that a recently built packet is > to memory before issuing the tx command to the NIC ? >=20 In short, i386 and amd64 architectures do bus snooping between the cpu = cache and the memory and bus controllers, and coherency is implicit and = guaranteed. No explicit barriers or flushes are needed for device = mastered DMA. Other CPU architectures have appropriate cache flushes = and memory barriers built into their busdma implementations. Note that = this is a different scenario than device register accesses, which is = essentially host mastered DMA. Scott
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