From nobody Sat Apr 6 20:17:37 2024 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4VBmqj6Fx6z5HGK4; Sat, 6 Apr 2024 20:17:37 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4VBmqj2JfPz4JwQ; Sat, 6 Apr 2024 20:17:37 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1712434657; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=rQ3a7Uybpgap/DROkftRRb8iVlniGaojbWKgyF7aObI=; b=lnnvHvNd6zyvbONsfNnIQfVeScbRIi17XVgRve1/X7+sEA5AAsTSAf/poTL9vw+BJ9KmvI 9XulX8/eQweFJG3uf4OHgo4AMXkED/NDt1QNNFFo9+ry+5l/OKlZNawDyu72qkuWM41mxP 1waq+bLJ+vEMYBBEUfY85T6/s3Jr3cWD2syzjwYDtrlCegARS+goHSO0sXCIgyS/6kqkZJ 5aKG/nFkYxoWXvQYemaKVxBzU8iy8dMMLU1zbKGR/hyLSp12Btkr61HAU73wCQrXraft9U YChVTo1+R/PM2AYcYckerypr5uJxExR5oIx3ifF/8nNbRKraOL1hHb8/uIZTaA== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1712434657; a=rsa-sha256; cv=none; b=GYdJa+FGRYyAIcrFCR4pbS5yfXxKm1dp85Jzl2SfMGEL8jwlAEU7+zPMxsCsW6maOSL1wa VqJRi24zuk/cmsHKz2vZk+OX5Hv0LETMWDhGeky0FJVip+9KiILxP2ZdwB4pVWK/6RWq5c d6vFOSkc6jXzs7CalcpM7TdU+6m2GEE2GsOPJZpbUEURq+NPXAVnM3qpbGnpflzmoPmK4C DAMXvoL3GAzVEawOAipXqf2NmysCCboBOSmbTkOGp3USrn3YO1klk1ZRbOOznvo+2UcD+Z dZ7uy3FSIsG9Cg/k3ARvi79Xfjn/RO3aNH0C177sltxxZHYqoxtMY1lG5rBOzQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1712434657; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=rQ3a7Uybpgap/DROkftRRb8iVlniGaojbWKgyF7aObI=; b=sfL2HenuoxJke/IFznLHQogSZJg9lKxaCfZW5auEZjJ7bf5Hlr8gni7i3XPDS7gZOZhmmI WpYH8rHLcJMyLzyuNHWtrXxNCfdI/qEVwtzbJVmAGmCYO5UBQqPTS+kKyuU+kqaxBUFX5w rAkaCz7auSEg30oNQ4GZKiaM+XqoPoQUCW6+RNS3AQJgrvbj4wBw27V2cvb+S7o7HV9cQp mEjwyBL/Uxh6Xho0loRolPBuezeSsiqgbTdAle8YlAgKzWyIi8VjgVzRu/+mLSDGICLG7L /zmbJPF0DpbeLlMQG0oiCwmc+qKtgmOZNRGS9KF+YMHdZWD7JaLB2eGq4sGPrw== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4VBmqj1sF2zxg8; Sat, 6 Apr 2024 20:17:37 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.17.1/8.17.1) with ESMTP id 436KHbfc029420; Sat, 6 Apr 2024 20:17:37 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.17.1/8.17.1/Submit) id 436KHbPn029418; Sat, 6 Apr 2024 20:17:37 GMT (envelope-from git) Date: Sat, 6 Apr 2024 20:17:37 GMT Message-Id: <202404062017.436KHbPn029418@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Dimitry Andric Subject: git: edc2dc17b1f2 - main - Revert commit 0e46b49de433 from llvm-project (by Matt Arsenault): List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-main@freebsd.org X-BeenThere: dev-commits-src-main@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: dim X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: edc2dc17b1f2dfe45dc85e6cc0ff54bca1ac8214 Auto-Submitted: auto-generated The branch main has been updated by dim: URL: https://cgit.FreeBSD.org/src/commit/?id=edc2dc17b1f2dfe45dc85e6cc0ff54bca1ac8214 commit edc2dc17b1f2dfe45dc85e6cc0ff54bca1ac8214 Author: Dimitry Andric AuthorDate: 2024-01-02 16:07:31 +0000 Commit: Dimitry Andric CommitDate: 2024-04-06 20:13:11 +0000 Revert commit 0e46b49de433 from llvm-project (by Matt Arsenault): Reapply "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" This reverts commit c398fa009a47eb24f88383d5e911e59e70f8db86. PPC backend was fixed in 2f82662ce901c6666fceb9c6c5e0de216a1c9667 Since it causes an assertion failure building /sys/dev/fb/vga.c: https://github.com/llvm/llvm-project/issues/76416 PR: 276104 MFC after: 1 month --- .../llvm/lib/CodeGen/RegisterCoalescer.cpp | 51 ++++------------------ 1 file changed, 9 insertions(+), 42 deletions(-) diff --git a/contrib/llvm-project/llvm/lib/CodeGen/RegisterCoalescer.cpp b/contrib/llvm-project/llvm/lib/CodeGen/RegisterCoalescer.cpp index 3fbb93795075..cbb1a74049fb 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -305,11 +305,7 @@ namespace { /// number if it is not zero. If DstReg is a physical register and the /// existing subregister number of the def / use being updated is not zero, /// make sure to set it to the correct physical subregister. - /// - /// If \p IsSubregToReg, we are coalescing a DstReg = SUBREG_TO_REG - /// SrcReg. This introduces an implicit-def of DstReg on coalesced users. - void updateRegDefsUses(Register SrcReg, Register DstReg, unsigned SubIdx, - bool IsSubregToReg); + void updateRegDefsUses(Register SrcReg, Register DstReg, unsigned SubIdx); /// If the given machine operand reads only undefined lanes add an undef /// flag. @@ -1347,7 +1343,8 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, if (DstReg.isPhysical()) { Register NewDstReg = DstReg; - unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(), DefSubIdx); + unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(), + DefMI->getOperand(0).getSubReg()); if (NewDstIdx) NewDstReg = TRI->getSubReg(DstReg, NewDstIdx); @@ -1496,7 +1493,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, MRI->setRegClass(DstReg, NewRC); // Update machine operands and add flags. - updateRegDefsUses(DstReg, DstReg, DstIdx, false); + updateRegDefsUses(DstReg, DstReg, DstIdx); NewMI.getOperand(0).setSubReg(NewIdx); // updateRegDefUses can add an "undef" flag to the definition, since // it will replace DstReg with DstReg.DstIdx. If NewIdx is 0, make @@ -1816,7 +1813,7 @@ void RegisterCoalescer::addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx, } void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg, - unsigned SubIdx, bool IsSubregToReg) { + unsigned SubIdx) { bool DstIsPhys = DstReg.isPhysical(); LiveInterval *DstInt = DstIsPhys ? nullptr : &LIS->getInterval(DstReg); @@ -1856,8 +1853,6 @@ void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg, if (DstInt && !Reads && SubIdx && !UseMI->isDebugInstr()) Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI)); - bool FullDef = true; - // Replace SrcReg with DstReg in all UseMI operands. for (unsigned i = 0, e = Ops.size(); i != e; ++i) { MachineOperand &MO = UseMI->getOperand(Ops[i]); @@ -1865,13 +1860,9 @@ void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg, // Adjust flags in case of sub-register joins. We don't want to // turn a full def into a read-modify-write sub-register def and vice // versa. - if (SubIdx && MO.isDef()) { + if (SubIdx && MO.isDef()) MO.setIsUndef(!Reads); - if (!Reads) - FullDef = false; - } - // A subreg use of a partially undef (super) register may be a complete // undef use now and then has to be marked that way. if (MO.isUse() && !DstIsPhys) { @@ -1903,25 +1894,6 @@ void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg, MO.substVirtReg(DstReg, SubIdx, *TRI); } - if (IsSubregToReg && !FullDef) { - // If the coalesed instruction doesn't fully define the register, we need - // to preserve the original super register liveness for SUBREG_TO_REG. - // - // We pretended SUBREG_TO_REG was a regular copy for coalescing purposes, - // but it introduces liveness for other subregisters. Downstream users may - // have been relying on those bits, so we need to ensure their liveness is - // captured with a def of other lanes. - - // FIXME: Need to add new subrange if tracking subranges. We could also - // skip adding this if we knew the other lanes are dead, and only for - // other lanes. - - assert(!MRI->shouldTrackSubRegLiveness(DstReg) && - "this should update subranges"); - MachineInstrBuilder MIB(*MF, UseMI); - MIB.addReg(DstReg, RegState::ImplicitDefine); - } - LLVM_DEBUG({ dbgs() << "\t\tupdated: "; if (!UseMI->isDebugInstr()) @@ -2121,8 +2093,6 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { }); } - const bool IsSubregToReg = CopyMI->isSubregToReg(); - ShrinkMask = LaneBitmask::getNone(); ShrinkMainRange = false; @@ -2190,12 +2160,9 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { // Rewrite all SrcReg operands to DstReg. // Also update DstReg operands to include DstIdx if it is set. - if (CP.getDstIdx()) { - assert(!IsSubregToReg && "can this happen?"); - updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx(), false); - } - updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx(), - IsSubregToReg); + if (CP.getDstIdx()) + updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx()); + updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx()); // Shrink subregister ranges if necessary. if (ShrinkMask.any()) {