From owner-cvs-src@FreeBSD.ORG Fri Mar 14 03:44:44 2008 Return-Path: Delivered-To: cvs-src@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 1BA69106566B; Fri, 14 Mar 2008 03:44:44 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 080F18FC1C; Fri, 14 Mar 2008 03:44:44 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m2E3ih4p078123; Fri, 14 Mar 2008 03:44:43 GMT (envelope-from jhb@repoman.freebsd.org) Received: (from jhb@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m2E3ihbA078122; Fri, 14 Mar 2008 03:44:43 GMT (envelope-from jhb) Message-Id: <200803140344.m2E3ihbA078122@repoman.freebsd.org> From: John Baldwin Date: Fri, 14 Mar 2008 03:44:42 +0000 (UTC) To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org X-FreeBSD-CVS-Branch: HEAD Cc: Subject: cvs commit: src/sys/amd64/amd64 intr_machdep.c src/sys/i386/i386 intr_machdep.c X-BeenThere: cvs-src@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 Mar 2008 03:44:44 -0000 jhb 2008-03-14 03:44:42 UTC FreeBSD src repository Modified files: sys/amd64/amd64 intr_machdep.c sys/i386/i386 intr_machdep.c Log: Fix a silly bogon which prevented all the CPUs that are tagged as interrupt receivers from being given interrupts if any CPUs in the system were not tagged as interrupt receivers that I introduced when switching the x86 interrupt code to track CPUs via FreeBSD CPU IDs rather than local APIC IDs. In practice this only affects systems with Hyperthreading (though disabling HTT in the BIOS would workaround the issue) as that is the only case currently where one can have CPUs that aren't tagged as interrupt receivers. On a Dell SC1425 test box with 2 x Xeon w/ HTT (so 4 logical CPUs of which 2 were interrupt receivers) the result was that all device interrupts were sent to CPU 0. MFC after: 1 week Pointy hat to: jhb Revision Changes Path 1.36 +4 -4 src/sys/amd64/amd64/intr_machdep.c 1.31 +4 -4 src/sys/i386/i386/intr_machdep.c