From nobody Mon Jun 23 12:07:37 2025 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4bQmzt6Ls7z60GVH; Mon, 23 Jun 2025 12:07:38 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R10" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4bQmzt0TpLz3g6Y; Mon, 23 Jun 2025 12:07:38 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1750680458; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=SXs3qS7EWHUxuGN46gKVTdN7Ra73YP1tgsMQE6vnKok=; b=vGlfx1nSMbhj27NOnqeLDdtCcO3qQx8FZa09DdAJbRGYFZox+UfcRS3UnhMMIN9htfflxU sXpS4EHrkdsXr0626DB6gHXOj8OxB8/1L3yfplUcEC3WjK01SmRKe4qw4KDwUpai7IaeHx Xo8X7BHkW4xpfMMNrBQHBUI/guHAmIVAWvvWAjBPkQM5QKWczETr2V1lrl+qV1pZiFuxek vjKr5l7KRbV6JHEHKI/D4gFOgeqqgGQiuWBlNqljdR3pgBxI/P/WL86rat6z4mTMNoX8OW lcwHyNShEhrSLlyq/xv+VL7Vv2x1jY1O+teyUSE0yrlH+9r8TUr9/W67QriTYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1750680458; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=SXs3qS7EWHUxuGN46gKVTdN7Ra73YP1tgsMQE6vnKok=; b=nZZmj4SdiIcGEzGn6F4ryYSqJS2jYagU9BVZCKch9EeRw8R08FvsepsXV2IflX72gHTdsE bWi/8/QqBIMqd26k5NEoHYp9iKYMJmSLYCuMcVlJXEAFVcsx3kprzQhf0KujNrbMxBQgKm NGtJabJEIQ0TLaAmnCT09jDu5u101JGpukJgjLqvF+Vy15nkEc0ScU4dUgGRBI7I6aHw8s 1ktLHwbSH6YHY97tVeGF6DXuEbgi+4YIJSD2i4ylZZ7KViQly3szjyoRCf1sITGRigdIVr gDTD1Fj3pHQmijA7HtDrXche+WLh+klifBZWG2m+6bTWM7STr7OyRkrlElPDDw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1750680458; a=rsa-sha256; cv=none; b=qTUIUj42VNgndvQnBSsa4yidGwPPlXh2xTlAfVQA4Acmd2Qpw/UZsiemGL5+Q80BwyXWS+ RQec8DXBzr7+rCEv06tdRxCNOiL0/lcgAJ36/MBeu7mhMPWKE6PT0H8kHgehdIJ/bPqv7C f/pYiekd2UU3hgFJhXbWAHFThNXi1xLrClFxg1rCfQWPmHJijrq5l7hgLZYabmNLHIaq22 iY2FOb7OjGlR7OCDxakR3tAA/TJLdN+OmaLvZpSBKgPSzgg9Re7fRmvTG7A+dlrPCIoFNB cY4xjcRy6Im85MfUENBB7cgBULxgFeg2McAO+WSa5syP3055gmKu2xDuA4ZQRg== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4bQmzs6kHdz11sQ; Mon, 23 Jun 2025 12:07:37 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 55NC7b0V059306; Mon, 23 Jun 2025 12:07:37 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 55NC7bLf059303; Mon, 23 Jun 2025 12:07:37 GMT (envelope-from git) Date: Mon, 23 Jun 2025 12:07:37 GMT Message-Id: <202506231207.55NC7bLf059303@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: 128085a3e7f3 - main - arm64: Use ISS to search for a special register List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 128085a3e7f3afc2f89845e81730a1d2340b3f04 Auto-Submitted: auto-generated The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=128085a3e7f3afc2f89845e81730a1d2340b3f04 commit 128085a3e7f3afc2f89845e81730a1d2340b3f04 Author: Andrew Turner AuthorDate: 2025-06-23 10:15:14 +0000 Commit: Andrew Turner CommitDate: 2025-06-23 10:18:19 +0000 arm64: Use ISS to search for a special register Previously we would use part of the msr/mrs instruction to find what register was being asked for. This was the only use for these values. We now have ESR_EL1 ISS field values for the same register so can use this new value to find what register is asked for. This lets us remove the old reg field from struct mrs_user_reg. Add macros to keep the old KPI. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D50905 --- sys/arm64/arm64/identcpu.c | 18 ++++++++---------- sys/arm64/include/cpu.h | 16 ++++++++++++---- sys/arm64/vmm/vmm.c | 3 ++- 3 files changed, 22 insertions(+), 15 deletions(-) diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index c1960812928f..72ef94531f54 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -2195,7 +2195,6 @@ static const struct mrs_field mvfr1_fields[] = { #endif /* COMPAT_FREEBSD32 */ struct mrs_user_reg { - u_int reg; u_int iss; bool is64bit; size_t offset; @@ -2204,7 +2203,6 @@ struct mrs_user_reg { #define USER_REG(name, field_name, _is64bit) \ { \ - .reg = name, \ .iss = name##_ISS, \ .offset = __offsetof(struct cpu_desc, field_name), \ .fields = field_name##_fields, \ @@ -2497,12 +2495,12 @@ mrs_field_cmp(uint64_t a, uint64_t b, u_int shift, int width, bool sign) } bool -get_kernel_reg(u_int reg, uint64_t *val) +get_kernel_reg_iss(u_int iss, uint64_t *val) { int i; for (i = 0; i < nitems(user_regs); i++) { - if (user_regs[i].reg == reg) { + if (user_regs[i].iss == iss) { *val = CPU_DESC_FIELD(kern_cpu_desc, i); return (true); } @@ -2516,13 +2514,13 @@ get_kernel_reg(u_int reg, uint64_t *val) * do not exceed those in the mask. */ bool -get_kernel_reg_masked(u_int reg, uint64_t *valp, uint64_t mask) +get_kernel_reg_iss_masked(u_int iss, uint64_t *valp, uint64_t mask) { const struct mrs_field *fields; uint64_t val; for (int i = 0; i < nitems(user_regs); i++) { - if (user_regs[i].reg == reg) { + if (user_regs[i].iss == iss) { val = CPU_DESC_FIELD(kern_cpu_desc, i); fields = user_regs[i].fields; for (int j = 0; fields[j].type != 0; j++) { @@ -2539,12 +2537,12 @@ get_kernel_reg_masked(u_int reg, uint64_t *valp, uint64_t mask) } bool -get_user_reg(u_int reg, uint64_t *val, bool fbsd) +get_user_reg_iss(u_int iss, uint64_t *val, bool fbsd) { int i; for (i = 0; i < nitems(user_regs); i++) { - if (user_regs[i].reg == reg) { + if (user_regs[i].iss == iss) { if (fbsd) *val = CPU_DESC_FIELD(user_cpu_desc, i); else @@ -2694,7 +2692,7 @@ update_special_regs(u_int cpu) * HWCAPs are set the check for these is enough. */ void -update_special_reg(u_int reg, uint64_t clear, uint64_t set) +update_special_reg_iss(u_int iss, uint64_t clear, uint64_t set) { MPASS(hwcaps_set == false); /* There is no locking here, so we only support changing this on CPU0 */ @@ -2702,7 +2700,7 @@ update_special_reg(u_int reg, uint64_t clear, uint64_t set) MPASS(PCPU_GET(cpuid) == 0); for (int i = 0; i < nitems(user_regs); i++) { - if (user_regs[i].reg != reg) + if (user_regs[i].iss != iss) continue; clear_set_special_reg_idx(i, clear, set); diff --git a/sys/arm64/include/cpu.h b/sys/arm64/include/cpu.h index 2dd1a905b2b7..4ef01e9a47ed 100644 --- a/sys/arm64/include/cpu.h +++ b/sys/arm64/include/cpu.h @@ -232,10 +232,18 @@ void ptrauth_mp_start(uint64_t); /* Functions to read the sanitised view of the special registers */ void update_special_regs(u_int); -void update_special_reg(u_int reg, uint64_t, uint64_t); -bool get_kernel_reg(u_int, uint64_t *); -bool get_kernel_reg_masked(u_int, uint64_t *, uint64_t); -bool get_user_reg(u_int, uint64_t *, bool); +void update_special_reg_iss(u_int, uint64_t, uint64_t); +#define update_special_reg(reg, clear, set) \ + update_special_reg_iss(reg ## _ISS, clear, set) +bool get_kernel_reg_iss(u_int, uint64_t *); +#define get_kernel_reg(reg, valp) \ + get_kernel_reg_iss(reg ## _ISS, valp) +bool get_kernel_reg_iss_masked(u_int, uint64_t *, uint64_t); +#define get_kernel_reg_masked(reg, valp, mask) \ + get_kernel_reg_iss_masked(reg ## _ISS, valp, mask) +bool get_user_reg_iss(u_int, uint64_t *, bool); +#define get_user_reg(reg, valp, fbsd) \ + get_user_reg_iss(reg ## _ISS, valp, fbsd) void cpu_desc_init(void); diff --git a/sys/arm64/vmm/vmm.c b/sys/arm64/vmm/vmm.c index f28643db99d2..3082d2941221 100644 --- a/sys/arm64/vmm/vmm.c +++ b/sys/arm64/vmm/vmm.c @@ -245,7 +245,8 @@ vmm_regs_init(struct vmm_regs *regs, const struct vmm_regs *masks) { #define _FETCH_KERN_REG(reg, field) do { \ regs->field = vmm_arch_regs_masks.field; \ - if (!get_kernel_reg_masked(reg, ®s->field, masks->field)) \ + if (!get_kernel_reg_iss_masked(reg ## _ISS, ®s->field, \ + masks->field)) \ regs->field = 0; \ } while (0) _FETCH_KERN_REG(ID_AA64AFR0_EL1, id_aa64afr0);