From owner-freebsd-hackers Mon May 13 16:21:10 1996 Return-Path: owner-hackers Received: (from root@localhost) by freefall.freebsd.org (8.7.3/8.7.3) id QAA05685 for hackers-outgoing; Mon, 13 May 1996 16:21:10 -0700 (PDT) Received: from irz301.inf.tu-dresden.de (irz301.inf.tu-dresden.de [141.76.1.11]) by freefall.freebsd.org (8.7.3/8.7.3) with SMTP id QAA05650 Mon, 13 May 1996 16:20:49 -0700 (PDT) Received: from sax.sax.de by irz301.inf.tu-dresden.de (8.6.12/8.6.12-s1) with ESMTP id BAA27752; Tue, 14 May 1996 01:20:41 +0200 Received: by sax.sax.de (8.6.12/8.6.12-s1) with UUCP id BAA16082; Tue, 14 May 1996 01:20:39 +0200 Received: (from j@localhost) by uriah.heep.sax.de (8.7.5/8.6.9) id BAA02422; Tue, 14 May 1996 01:18:17 +0200 (MET DST) From: J Wunsch Message-Id: <199605132318.BAA02422@uriah.heep.sax.de> Subject: Re: Triton chipset with 256k cache caches 32M only? To: blh@nol.net (Brett L. Hawn) Date: Tue, 14 May 1996 01:18:16 +0200 (MET DST) Cc: mmead@Glock.COM, jgreco@brasil.moneng.mei.com, hackers@freebsd.org, hardware@freebsd.org Reply-To: joerg_wunsch@uriah.heep.sax.de (Joerg Wunsch) In-Reply-To: from "Brett L. Hawn" at "May 13, 96 01:24:52 pm" X-Phone: +49-351-2012 669 X-PGP-Fingerprint: DC 47 E6 E4 FF A6 E9 8F 93 21 E0 7D F9 12 D6 4E X-Mailer: ELM [version 2.4ME+ PL17 (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: owner-hackers@freebsd.org X-Loop: FreeBSD.org Precedence: bulk As Brett L. Hawn wrote: > I would highly suggest getting some of the new > ASUS (just my particular favorite) tr-2 chipset motherboards, these solve > the caching problem along with many of the other inherent bugs of tr-1 > chipsets. They even can do ECC now if you're using parity SIMMs! (About to get my new board into service by tomorrow or thursday. :) -- cheers, J"org joerg_wunsch@uriah.heep.sax.de -- http://www.sax.de/~joerg/ -- NIC: JW11-RIPE Never trust an operating system you don't have sources for. ;-)