From owner-svn-src-head@FreeBSD.ORG Wed Dec 23 17:54:24 2009 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 82775106568D; Wed, 23 Dec 2009 17:54:24 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 717BC8FC18; Wed, 23 Dec 2009 17:54:24 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id nBNHsOik004920; Wed, 23 Dec 2009 17:54:24 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id nBNHsOYO004918; Wed, 23 Dec 2009 17:54:24 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <200912231754.nBNHsOYO004918@svn.freebsd.org> From: Pyun YongHyeon Date: Wed, 23 Dec 2009 17:54:24 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r200905 - head/sys/dev/ste X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Dec 2009 17:54:24 -0000 Author: yongari Date: Wed Dec 23 17:54:24 2009 New Revision: 200905 URL: http://svn.freebsd.org/changeset/base/200905 Log: Reimplement controller reset. Datasheet says full reset takes about 1ms. Since we switched to memory register mapping make sure to flush PCI posted write by reading the register again. While I'm here add additional delays in loop while driver waits the completion of the reset. Modified: head/sys/dev/ste/if_ste.c Modified: head/sys/dev/ste/if_ste.c ============================================================================== --- head/sys/dev/ste/if_ste.c Wed Dec 23 17:46:11 2009 (r200904) +++ head/sys/dev/ste/if_ste.c Wed Dec 23 17:54:24 2009 (r200905) @@ -1731,20 +1731,27 @@ ste_stop(struct ste_softc *sc) static void ste_reset(struct ste_softc *sc) { + uint32_t ctl; int i; - STE_SETBIT4(sc, STE_ASICCTL, - STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| - STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| - STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| - STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| - STE_ASICCTL_EXTRESET_RESET); - - DELAY(100000); + ctl = CSR_READ_4(sc, STE_ASICCTL); + ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET | + STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET | + STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET | + STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET | + STE_ASICCTL_EXTRESET_RESET; + CSR_WRITE_4(sc, STE_ASICCTL, ctl); + CSR_READ_4(sc, STE_ASICCTL); + /* + * Due to the need of accessing EEPROM controller can take + * up to 1ms to complete the global reset. + */ + DELAY(1000); for (i = 0; i < STE_TIMEOUT; i++) { if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) break; + DELAY(10); } if (i == STE_TIMEOUT)