From owner-freebsd-mips@FreeBSD.ORG Tue Oct 4 16:06:27 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 1BEDD1065670; Tue, 4 Oct 2011 16:06:27 +0000 (UTC) (envelope-from aduane@juniper.net) Received: from exprod7og112.obsmtp.com (exprod7og112.obsmtp.com [64.18.2.177]) by mx1.freebsd.org (Postfix) with ESMTP id 53E0C8FC0C; Tue, 4 Oct 2011 16:06:25 +0000 (UTC) Received: from P-EMHUB01-HQ.jnpr.net ([66.129.224.36]) (using TLSv1) by exprod7ob112.postini.com ([64.18.6.12]) with SMTP; Tue, 04 Oct 2011 09:06:26 PDT Received: from P-EMHUB11-HQ.jnpr.net (172.24.192.58) by P-EMHUB01-HQ.jnpr.net (172.24.192.35) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 4 Oct 2011 09:04:51 -0700 Received: from p-emfe01-wf.jnpr.net (172.28.145.24) by P-EMHUB11-HQ.jnpr.net (172.24.192.58) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 4 Oct 2011 09:04:51 -0700 Received: from EMBX01-WF.jnpr.net ([fe80::1914:3299:33d9:e43b]) by p-emfe01-wf.jnpr.net ([fe80::d0d1:653d:5b91:a123%11]) with mapi; Tue, 4 Oct 2011 12:04:50 -0400 From: Andrew Duane To: Andrew Duane , Warner Losh , Adrian Chadd Date: Tue, 4 Oct 2011 12:04:48 -0400 Thread-Topic: svn commit: r225892 - head/sys/mips/mips Thread-Index: AcyCP0JNZHSCsecwTdWmNMj1qfWH+gAaiKLYAAFZGkA= Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "Jayachandran C." , Kostik Belousov , Alexander Motin , "freebsd-mips@freebsd.org" Subject: RE: svn commit: r225892 - head/sys/mips/mips X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Oct 2011 16:06:27 -0000 The MIPS manual volume 3 says there is a 3 cycle "typical" wait between an = MTC0 that messes with Status[IE] and an interrupted instruction. That hazar= d doesn't seem to apply here, to any of the cases we have. I do have a question: in StartWaitSkip, the value of Status[IE] is being to= ggled, not cleared. Is that correct? Do we always guarantee that it will be= set on entry here? I had also made a comment about the "PTR_ADDU k1, 16 # skip over wait" in M= ipsKernIntr; I think it would be safer (and clearer) to do "PTR_LA k1, EndW= aitSkip" instead. =A0................................... Andrew Duane Juniper Networks o=A0=A0=A0+1 978 589 0551 m=A0 +1 603-770-7088 aduane@juniper.net =A0 > -----Original Message----- > From: Andrew Duane > Sent: Tuesday, October 04, 2011 8:22 AM > To: Warner Losh; Adrian Chadd > Cc: Andrew Duane; Jayachandran C.; Kostik Belousov; Alexander Motin; > freebsd-mips@freebsd.org > Subject: Re: svn commit: r225892 - head/sys/mips/mips >=20 > Let me pull my MIPS manual when I get in. It exactly specifies the > hazards for each bit. >=20 > Warner Losh wrote: >=20 >=20 > On Oct 3, 2011, at 7:38 PM, Adrian Chadd wrote: >=20 > > On 4 October 2011 07:09, Andrew Duane wrote: > >> The COP0_SYNC's should be there (should there also be one after the > MTC0 in MipsKernIntr?). The ISA says a hazard is needed, so that should > be reflected. I assume different platforms define COP0_SYNC for > themselves as needed? > > > > Is one needed after the mtc0 after StartWaitSkip? >=20 > I don't think it matters. The COP0_SYNC is needed when you want to > flush the instruction pipeline so that changes to COP0 don't affect > them 'randomly'. However, in this case. Either we're setting a bit > that's already set, which won't change anything, or we're setting a bit > that's clear, which will just delay the delivery of the interrupt a few > cycles. The race where it happens before the wait instruction is > handled by the rest of the patch. >=20 > Warner