Skip site navigation (1)Skip section navigation (2)
Date:      Wed, 06 Jun 2018 14:19:58 +0000
From:      bugzilla-noreply@freebsd.org
To:        ports-bugs@FreeBSD.org
Subject:   [Bug 227591] [NEW PORT] devel/yosys - Verilog RTL syntensis
Message-ID:  <bug-227591-7788-SHwrW6eCGD@https.bugs.freebsd.org/bugzilla/>
In-Reply-To: <bug-227591-7788@https.bugs.freebsd.org/bugzilla/>
References:  <bug-227591-7788@https.bugs.freebsd.org/bugzilla/>

next in thread | previous in thread | raw e-mail | index | archive | help
https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D227591

--- Comment #2 from commit-hook@freebsd.org ---
A commit references this bug:

Author: tobik
Date: Wed Jun  6 14:19:52 UTC 2018
New revision: 471844
URL: https://svnweb.freebsd.org/changeset/ports/471844

Log:
  New port: devel/yosys

  Yosys is a framework for Verilog RTL synthesis.  It currently has
  extensive Verilog-2005 support and provides a basic set of synthesis
  algorithms for various application domains.

  WWW: http://www.clifford.at/yosys/

  PR:           227591
  Submitted by: Johnny Sorocil <jsorocil@gmail.com>
  Differential Revision:        https://reviews.freebsd.org/D15632

Changes:
  head/devel/Makefile
  head/devel/yosys/
  head/devel/yosys/Makefile
  head/devel/yosys/distinfo
  head/devel/yosys/pkg-descr
  head/devel/yosys/pkg-plist

--=20
You are receiving this mail because:
You are the assignee for the bug.=



Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?bug-227591-7788-SHwrW6eCGD>